Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product costs in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. Artech House Publishers Wafer-Level Testing and Test During Burn-In for Integrated Circuits 2 Contents 8 Preface 14 Acknowledgements 16 Chapter 1 Introduction 18 1.1 BACKGROUND 21 1.1.1 System-Level Design-for-Test and Test Scheduling for Core-Based SoCs 21 1.1.2 Wafer-Level Test During Burn-In 23 1.1.3 Scan Design 26 1.2 KEY DRIVERS FORWAFER-LEVEL TEST AND BURN-IN 26 1.2.1 Challenges Associated withWafer Sort 27 1.2.2 Emergence of KGDs 28 1.2.3 WLTBI: Industry Adoption and Challenges 28 1.3 WAFER-LEVEL TEST PLANNING FOR CORE-BASED SOCS 33 1.4 WAFER-LEVEL DEFECT SCREENING FOR MIXED-SIGNAL SOCS 34 1.5 WLTBI OF CORE-BASED SOCS 34 1.6 POWER MANAGEMENT FOR WLTBI 35 1.7 HOWTHIS BOOK IS ORGANIZED 35 References 37 Chapter 2 Wafer-Level Test and Burn-In: Industry Practices and Trends 42 2.1 OVERVIEW AND DEFINITIONS 42 2.2 STATUS OFWAFER-LEVEL TEST AND WLBI 46 2.2.1 Wafer-Level Burn-In 48 2.3 DOING BOTH WAFER-LEVEL TEST AND WAFER-LEVEL BURN IN 50 2.4 PRACTICAL MATTERS 51 2.4.1 Volumes Needed 51 2.4.2 Power per Die and perWafer 53 2.4.3 Types of Die That Can Be Tested and Burned-In 53 2.4.4 Functional Tests Versus Parametric Tests 53 2.4.5 Number of Contacts per Die 54 2.4.6 Number of Signal Channels Needed 54 2.4.7 Single-Pass Versus Multiple Pass 55 2.4.8 Maximum Force per Wafer 55 2.4.8 Maximum Force per Wafer 55 2.4.9 ContactMethod 56 2.4.10 Contact Life 57 2.4.11 Minimizing Costs for SDBs and Contactors 58 2.4.12 Bumped Wafers Versus Wafers with Bond Pads 58 2.4.13 Pitch 58 2.4.14 Pad Size 59 2.4.15 Coplanarity 60 2.4.16 Background (Thinned) Wafers and Plastic-Backed Wafers 60 2.4.17 More Than One Die Type on the Wafer 60 2.4.18 Changing Cartridges 60 2.4.19 Test Electronics 61 2.4.20 Die Power and Shorted Die 61 2.4.21 Current per Die and per Wafer 61 2.4.22 Voltage Levels Needed 62 2.4.23 Clock and Pattern Frequencies 62 2.4.24 Wafer Maps and Binning 62 2.5 FUTURE PROJECTIONS 62 References 63 Chapter 3 Resource-Constrained Testing of Core-Based SoCs 66 3.1 DEFECT PROBABILITY ESTIMATION FOR EMBEDDED CORES 68 3.1.1 Unified Negative-Binomial Model for Yield Estimation 68 3.1.2 Procedure to Determine Core Defect Probabilities 69 3.2 TEST-LENGTH SELECTION FOR WAFER-LEVEL TEST 73 3.2.1 Test-Length Selection Problem: PTLS 77 3.2.2 Efficient Heuristic Procedure 79 3.2.3 Greedy Heuristic Procedure 81 3.3 EXPERIMENTAL RESULTS 82 3.3.1 Approximation Error in PrS Due to Taylor Series Approximation 85 3.4 TEST DATA SERIALIZATION 89 3.4.1 Test-Length and TAM Optimization Problem: PTLTWS 91 3.4.2 Experimental Results: PTLTWS 93 3.4.3 Enumeration-Based TAM Width and Test-Length Selection 97 3.4.4 TAM Width and Test-Length Selection Based on Geometric Programming 100 3.4.5 Approximation Error in PrS 104 3.5 SUMMARY 105 References 106 Chapter 4 Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs 108 4.1 TEST WRAPPER FOR ANALOG CORES 109 4.1.1 Analog Test Wrapper Modes 111 4.2 WAFER-LEVEL DEFECT SCREENING: MIXED-SIGNAL CORES 111 4.2.1 Signature Analysis: Mean-Signature-Based Correlation (MSBC) 113 4.2.2 Signature Analysis: Golden-Signature-Based Correlation (GSBC) 114 4.3 GENERIC COST MODEL 117 4.3.1 Correction Factors: Test Escapes and Yield Loss 117 4.3.2 Cost Model: Generic Framework 119 4.3.3 Overall Cost Components 120 4.4 COST MODEL: QUANTITATIVE ANALYSIS 121 4.4.1 Cost Model: Results for ASIC Chip K 122 4.4.2 Cost Model: Results Considering Failures Due to Both Digital and Mixed-Signal Cores 123 4.4.3 Cost Model: Results Considering Failure Distributions 125 4.5 SUMMARY 130 4.6 ACKNOWLEDGMENTS 131 References 131 Chapter 5 Wafer-Level Test During Burn-In: TestScheduling for Core-Based SOCs 134 5.1 CYCLE-ACCURATE POWER MODELING 136 5.1.1 Transitions in a Scan Chain 137 5.1.2 Transitions in Wrapper Chains 141 5.2 TEST SCHEDULING FOR WLTBI 142 5.2.1 Graph-Matching-Based Approach for Test Scheduling 143 5.3 HEURISTIC PROCEDURE TO SOLVE PCORE ORDER 148 5.4 BASELINE METHODS 149 5.5 EXPERIMENTAL RESULTS 149 5.6 SUMMARY 156 5.7 ACKNOWLEDGMENTS 156 References 156 Chapter 6 Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering 158 6.1 BACKGROUND: CYCLE-ACCURATE POWER MODELING 159 6.1.1 Scan-Chain Transition-Count Calculation 159 6.2 TEST-PATTERN ORDERING PROBLEM: PTPO 161 6.2.1 Computational Complexity of PTPO 164 6.3 HEURISTIC METHODS FOR TEST-PATTERN ORDERING 165 6.4 BASELINE APPROACHES 167 6.4.1 Baseline Method 1: Average Power Consumption 167 6.4.2 Baseline Method 2: Peak Power Consumption 168 6.5 EXPERIMENTAL RESULTS 168 6.6 SUMMARY 172 References 177 Chapter 7 Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation 180 7.1 MINIMUM-VARIATION X-FILL PROBLEM: PMV F 181 7.1.1 Metrics: Variation in Power Consumption During Test 181 7.1.2 Outline of Proposed Method 182 7.2 FRAMEWORK TO CONTROL POWER VARIATION FOR WLTBI 183 7.2.1 Minimum-Variation X-Filling 183 7.2.2 Eliminating Capture-Power Violations 186 7.2.3 Test-Pattern Ordering for WLTBI 187 7.2.4 Complete Procedure 188 7.3 BASELINE APPROACHES 189 7.3.1 Baseline Method 1: Adjacent Fill 189 7.3.2 Baseline Method 2: 0-Fill 191 7.3.3 Baseline Method 3: 1-Fill 191 7.3.4 Baseline Method 4: ATPG-Compacted Test Sets 191 7.4 EXPERIMENTAL RESULTS 192 7.5 SUMMARY 198 References 199 Chapter 8 Conclusions 200 8.1 SUMMARY 200 8.2 FUTURE WORK 202 8.2.1 Integrated Test-Length and Test-Pattern Selection for Core-Based SoCs 202 8.2.2 Multiple Scan-Chain Design for WLTBI 203 8.2.3 Layout-Aware SoC Test Scheduling for WLTBI 203 References 204 List of Symbols 206 List of Acronyms 208 About the Authors 212 Index 214 1596939893,9781596939899