VLSI-SoC : design and engineering of electronics systems based on new computing paradigms : 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and extended selected pa

This book contains extended and revised versions of the best papers presented at the 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, held in Verona, Italy, in October 2018. The 13 full papers included in this volume were carefully reviewed and selected from the 27 papers (out of 106 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems. Preface 6 Organization 8 Contents 14 A 65nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load 16 1 Introduction 16 2 Proposed Synthesizable LDO 18 2.1 Architecture 18 2.2 Transfer Function of the Control Loop 21 2.3 Design Procedure of the Proposed LDO 22 3 Prototype Implementation and Measurement Results 24 4 Conclusion 26 References 27 An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication 29 1 Introduction 29 2 Pulsed-Signaling Techniques 31 3 Pulsed-Index Communication Interface Architecture (PICIA) 31 3.1 Register Set 32 3.2 Instruction Formats 32 3.3 Addressing Modes 33 3.4 Interrupts 33 3.5 External I/O 34 4 PICIA Assembly Language 34 4.1 Type 1 Instructions (I-Type 1) 35 4.2 Type 2 Instructions (I-Type 2) 38 4.3 Type 3 Instructions (I-Type 3) 38 5 Experimental Verification and Results 40 6 Securing PICIA 42 6.1 Extended Register Set 43 6.2 Extended Instruction Set 43 6.3 Instruction Format 44 7 Conclusions 45 References 46 The Connection Layout in a Lattice of Four-Terminal Switches 47 1 Introduction 47 2 Rearranging the Lattice 50 2.1 Solving Problem1 51 2.2 Hardness of Problem1 53 2.3 Solving Problem2 53 2.4 Hardness of Problem2 55 3 Solving Problem3 57 3.1 Impossible Instances 59 3.2 Hardness of Problem3 60 3.3 Heuristics for Problem3 61 4 Experimental Results 64 5 Concluding Remarks 66 References 66 Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS 68 1 Introduction 69 2 Parallel Memories: Challenges and Solutions 71 2.1 Parallel Memories 71 2.2 The Polymorphic Register File and PolyMem 72 2.3 Matrix Storage in a Parallel Memory 74 3 Implementation Details 75 4 Evaluation and Results 76 4.1 Experimental Setup 76 4.2 Results 78 5 Application Case-Studies 81 5.1 Matrix Multiplication (MM) 82 5.2 Markov Chain and the Matrix Power Operation 84 6 Related Work 88 7 Conclusion and Future Work 90 References 90 Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields 94 1 Introduction 94 1.1 Problem Description, Objectives, and Contributions 96 2 Review of Previous Work 97 3 Preliminaries: Notation and Background Results 98 4 Algebraic Miter for Equivalence Checking 102 5 Formulating the Rectification Check 104 5.1 Single Fix Rectification 104 6 Craig Interpolants in Finite Fields 108 6.1 Computing a Rectification Function from Craig Interpolants 110 7 Efficient Gröbner Basis Computations for EL and EH 112 8 Experimental Results 115 9 Conclusion 118 References 118 Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis 122 1 Introduction 122 2 Related Works 124 2.1 Adaptive ConvNets 125 2.2 Fixed-Point Quantization 126 3 Energy-Accuracy Scalable Convolution 126 3.1 SW: Multiprecision Convolution 127 3.2 HW: Variable-Latency Processing Element 128 3.3 Hardware Characterization 129 4 Energy-Driven Precision Assignment 130 4.1 Fixed-Point Quantization 130 4.2 Multiprecision Fixed-Point ConvNets 131 5 Results 134 5.1 Experimental Set-up 134 5.2 Benchmarks 135 5.3 Results 136 6 Conclusions 139 References 140 ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code 143 1 Introduction 143 2 Preliminaries 145 2.1 Galois Field Arithmetic 146 2.2 Basics of BCH Encoding and Decoding Operation 147 2.3 In-Memory Computing Using ReRAM 148 3 Methodology 150 3.1 Generation of GF Elements 151 3.2 Encoding and Decoding Operations 153 4 Experiment 154 5 Conclusion 159 References 159 Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems 162 1 Introduction 162 2 Background and Related Work 164 2.1 Memristor 164 2.2 Memristor Aided LoGIC (MAGIC) 164 2.3 In-Memory Computation Using Memristor Crossbar 165 2.4 Fanout 165 3 Proposed Approach 166 3.1 Overall Approach: Case 1 167 3.2 Mapping Scenario Analysis: Case 1 167 3.3 Overall Approach: Case 2 173 3.4 Mapping Scenario Analysis: Case 2 173 4 Experimental Results 176 4.1 Experimental Setup 177 4.2 Results and Analysis 178 5 Conclusions 180 References 181 Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis 182 1 Introduction 182 2 Background 184 2.1 Target Application: Neural Network Simulation 184 2.2 Target Architecture: Neuromorphic MPSoCs Board 185 3 Problem Formulation 188 3.1 Problem Relaxation 189 3.2 Graph Partitioning 190 4 Placement 191 4.1 Naïve Placement 191 4.2 Spectral Embedding 191 4.3 Scotch 192 4.4 Simulated Annealing 193 5 Results 194 6 Conclusions 199 References 200 Improved Test Solutions for COTS-Based Systems in Space Applications 202 Abstract 202 1 Introduction 202 2 The MaMMoTH-Up System 204 2.1 General Architecture and Functions 204 2.2 The OR1200 Processor 206 2.3 The UART Core 207 3 Comparing the Functional and the Structural Approaches 207 3.1 Background 207 3.2 The Functional Test 208 3.3 The Structural Test 209 3.4 Results 212 4 Safe Faults 213 4.1 Safe Faults Identification 214 4.2 Results 217 5 Conclusions 219 Acknowledgments 219 References 220 Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection 222 1 Introduction 223 2 Memories Based on STT-MRAM 225 3 Read and Write Operations of STT-MRAM Cells 226 3.1 Read Operation 227 3.2 Write Operation 227 4 Write Time Definition for an STT-MRAM Cell 228 5 Analysis of STT-MRAM Behavior Under Short Defects 229 5.1 Defect Model for Short Defects in the STT-MRAM 230 5.2 Impact of Short Defects on Write Operation 230 5.3 Impact of Short Defects on the Read Operation 232 5.4 Summary Behavior of Write and Read Operation Under Short Defects 235 6 Proposed Test Technique 235 6.1 Fundamental of the Proposed Test Technique 235 6.2 Proposed Test Circuitry 238 7 Cost and Comparison of Our Proposal with Logic Test 240 7.1 Detection Probability Comparison 240 7.2 Hardware Comparison 242 7.3 Other Issues 243 7.4 Short Defects that Can Be Detected 243 8 Conclusions 244 References 244 Assessment of Low-Budget Targeted Cyberattacks Against Power Systems 247 1 Introduction 247 2 Background 251 2.1 Power Systems 251 2.2 Protection and Control Equipment 253 2.3 Grid Modernization 253 2.4 Global Positioning System 255 3 Open Sourcing Power System Cyberattacks 255 3.1 Threat Model 256 3.2 Open Source Intelligence for Modeling Power Systems 256 3.3 Identifying Critical Locations with Contingency Analysis 257 3.4 Open Source Exploitation - OSEXP 258 3.5 Instantiation of an OSEXP Attack: GPS Time Spoofing Against PMUs 259 4 Experimental Evaluation 261 4.1 Power System Modeling 261 4.2 GPS Experimental Setup 264 4.3 Budget 267 5 Conclusions 268 References 268 Efficient Hardware/Software Co-design for NTRU 272 1 Introduction 272 2 Related Works 275 3 NTRU 276 3.1 Notation 276 3.2 Short Vector Encryption Scheme (SVES) 276 3.3 NTRU with SVES 277 4 NTRU Full Hardware Architecture 278 4.1 Convolution (CONV) 279 4.2 Blinding Polynomial Generation Method (BPGM) 280 4.3 Mask Generation Function (MGF) 281 4.4 Modulo Reduction (MOD P) 281 5 NTRU HW/SW Co-design 282 5.1 Software Implementation 283 6 Security Analysis 284 6.1 Optimized Architecture 284 6.2 Vulnerabilities 285 7 Results 289 7.1 Results of Full Hardware Implementation 289 7.2 Results of HW/SW Co-design 290 8 Conclusion 294 References 294 Author Index 296 Front Matter ....Pages i-xiv A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load (Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada)....Pages 1-13 An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication (Shahzad Muzaffar, Ibrahim (Abe) M. Elfadel)....Pages 14-31 The Connection Layout in a Lattice of Four-Terminal Switches (Anna Bernasconi, Antonio Boffa, Fabrizio Luccio, Linda Pagli)....Pages 32-52 Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS (L. Stornaiuolo, M. Rabozzi, M. D. Santambrogio, D. Sciuto, C. B. Ciobanu, G. Stramondo et al.)....Pages 53-78 Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields (Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu)....Pages 79-106 Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis (Valentino Peluso, Andrea Calimera)....Pages 107-127 ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code (Swagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay)....Pages 128-146 Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems (Md Adnan Zaman, Rajeev Joshi, Srinivas Katkoori)....Pages 147-166 Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis (Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva)....Pages 167-186 Improved Test Solutions for COTS-Based Systems in Space Applications (Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, Jan-Gerd Mess)....Pages 187-206 Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection (Victor Champac, Andres Gomez, Freddy Forero, Kaushik Roy)....Pages 207-231 Assessment of Low-Budget Targeted Cyberattacks Against Power Systems (XiaoRui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos)....Pages 232-256 Efficient Hardware/Software Co-design for NTRU (Tim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda)....Pages 257-280 Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications (Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sanchez, Matteo Sonza Reorda, Jan-Gerd Mess)....Pages C1-C1 Back Matter ....Pages 281-281