VLSI Placement and Global Routing Using Simulated Annealing (The Springer International Series in Engineering and Computer Science, 54)

From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re­ ceived a copy of the original IBM internal report on simulated annealing approximately the day of its release. Given my background in statistical mechanics and solid state physics, I was immediately impressed by this new combinatorial optimization technique. As Prof. Sangiovanni-Vincentelli had suggested I work in the areas of placement and routing, it was in these realms that I sought to explore this new algorithm. My flJ'St implementation of simulated annealing was for an island-style gate array placement problem. This work is presented in the Appendix of this book. I was quite struck by the effect of a nonzero temperature on what otherwise appears to be a random in­ terchange algorithm. Front Matter....Pages i-xxvi Introduction....Pages 1-30 The Simulated Annealing Algorithm....Pages 31-49 Placement and Global Routing of Standard Cell Integrated Circuits....Pages 51-91 Macro/Custom Cell Chip-Planning, Placement, and Global Routing....Pages 93-139 Average Interconnection Length Estimation....Pages 141-179 Interconnect-Area Estimation for Macro Cell Placements....Pages 181-198 An Edge-Based Channel Definition Algorithm for Rectilinear Cells....Pages 199-228 A Graph-Based Global Router Algorithm....Pages 229-246 Conclusion....Pages 247-253 Back Matter....Pages 255-278