VLSI design and test : 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, revised selected papers

This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology. Front Matter....Pages - Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM....Pages 1-9 A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator....Pages 10-18 A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier....Pages 19-25 An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network....Pages 26-34 Computational Functions’ VLSI Implementation for Compressed Sensing....Pages 35-43 A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization....Pages 44-48 An Area Efficient Wide Range On-Chip Delay Measurement Architecture....Pages 49-58 10 Gbps Current Mode Logic I/O Buffer....Pages 59-65 Kapees: A New Tool for Standard Cell Placement....Pages 66-73 Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization....Pages 74-82 Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence....Pages 83-93 Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application....Pages 94-99 Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology....Pages 100-107 Characterization of Logical Effort for Improved Delay....Pages 108-117 A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance....Pages 118-127 An Improved g m / I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design....Pages 128-137 An Efficient RF Energy Harvester with Tuned Matching Circuit....Pages 138-145 A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-T ox in CMOS VLSI Circuits....Pages 146-152 Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET....Pages 153-159 Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)....Pages 160-168 Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs....Pages 169-176 A Combined CMOS Reference Circuit with Supply and Temperature Compensation....Pages 177-184 Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology....Pages 185-193 A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures....Pages 194-203 Random-LRU: A Replacement Policy for Chip Multiprocessors....Pages 204-213 Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations....Pages 214-222 Congestion Balancing Global Router....Pages 223-232 CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions....Pages 233-241 Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption....Pages 242-248 Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive Accelerometer....Pages 249-256 CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time....Pages 257-266 Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High- k Spacers....Pages 267-273 On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics....Pages 274-283 Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool....Pages 284-293 A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup....Pages 294-303 Fault Aware Dynamic Adaptive Routing Using LBDR....Pages 304-311 Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals....Pages 312-321 On Designing Testable Reversible Circuits Using Gate Duplication....Pages 322-329 Circuit Transient Analysis Using State Space Equations....Pages 330-336 3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter....Pages 337-344 Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP....Pages 345-352 Design and Optimization of a 2x2 Directional Microstrip Patch Antenna....Pages 353-360 A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips....Pages 361-375 Defect Diagnosis of Digital Circuits Using Surrogate Faults....Pages 376-386 Back Matter....Pages -