The Simple Art of SoC Design : Closing the Gap Between RTL and ESL

This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow’s SoC designs. \* Provides an easily accessible guide that enables readers to write better, more verifiable code for complex SoCs; \* Describes techniques for successful SoC design, including simplifying RTL design, reducing complexity in control-dominated designs, reducing complexity in data path dominated designs, and simplifying interfaces; \* Discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages should develop to fill future needs. Early praise for The Simple Art of SoC Design... I have enjoyed reading and reviewing the draft material for this book as Mike has developed and refined the content. His clarity and insight, gained from working with a range of mutual customers and SOC designers, shines through. Working in an industry where successful IP deployment is fundamental to product success, I found that this book addresses practically what the designer must focus on, from specification, partitioning and clean interfacing through implementation to verification. Highly recommended whether you are newly starting out in SoC design, or you are an industry veteran weighed down with ever more complex system integration challenges. David Flynn Fellow, Research & Development, ARM Ltd Part-Time Visiting Professor in Electronics and Computer Science, University of Southampton, UK Guidelines for Datapath Synthesis......Page 3 Mixed Unsigned/Signed Expression......Page 5 Cluster Datapath Portions......Page 7 Complementing an Operand......Page 9 C Version......Page 13 Cover......Page 1 The SimpleArt of SoC Design......Page 4 Disclaimer......Page 6 Preface......Page 10 Raising the Level of Abstraction of RTL......Page 11 Fork and Join......Page 12 Interfaces......Page 2 Foreword......Page 8 Contents......Page 14 Final RTL Version......Page 15 Gates per Line of Code......Page 17 Canonical Design......Page 18 Summary......Page 16 The Problem......Page 19 Divide and Conquer......Page 21 Tightly Coupled vs. Loosely Coupled Systems......Page 25 Proposal – New Data Types......Page 26 Sequential and Combinational Processes......Page 27 The Challenge of Verification......Page 28 The Pursuit of Simplicity......Page 29 Structure of This Book......Page 30 Challenges......Page 32 Syntactic Fluff......Page 33 Concurrency and State Space......Page 34 Reference for Examples......Page 35 Techniques......Page 36 Encapsulating Combinational Code......Page 37 Structuring Sequential Code......Page 38 Interfaces......Page 41 Thinking High-level......Page 42 FIFOs......Page 43 Chapter 3: Reducing Complexity in Control-Dominated Designs......Page 44 Original Code......Page 45 Preprocessing Sequential Code......Page 49 Preprocessing Combinational Code......Page 51 The General Model......Page 22 Rule of Seven......Page 24 Using High Level Data Types......Page 40 State Space in the Original Design......Page 46 Comments......Page 47 Recoding the State Machine......Page 52 Relocating Other Sequential Code......Page 54 Rewriting Combinational Code......Page 55 Analyzing the New Code......Page 57 System Verilog......Page 58 Simplified Block Diagram......Page 60 Summary......Page 61 General Model for HFSMs......Page 63 Converting the BCU to a HFSM......Page 67 Input, Output, and Internal State Space......Page 71 Preliminary Calculations of State Space......Page 72 Shallow vs. Deep State Space......Page 74 The Cross Product of State Spaces......Page 76 Encapsulating Sequential Code......Page 79 State Machines as Sequential Processes......Page 80 Examples......Page 81 Input State Space......Page 84 State Space for Hierarchical State Machines......Page 85 Chapter 6: Verification......Page 86 Some Simple Examples of Verifiable Designs......Page 87 Verification Overview......Page 88 Goals of Complete Verification......Page 89 Verifying State Machines......Page 90 Example: The BCU......Page 92 Structure of the Canonical Design......Page 95 Separating Data from Control......Page 96 Verifying the Control Path: The State Machine......Page 97 Line Coverage......Page 98 Input State Coverage......Page 99 Data Path Uniqueness......Page 100 Verifying the Data Path Algorithm......Page 101 Chapter 7: Reducing Complexity in Data Path Dominated Designs......Page 103 Problems and Limitations in the Original Code......Page 105 Minimizing Lines of Code......Page 106 Other Versions of the Code......Page 110 Task Version......Page 111 More Code Size Reduction......Page 112 Untimed Version......Page 114 Experimental Versions......Page 116 Reference Versions......Page 117 Synthesis Results......Page 119 Canonical Design......Page 120 Summary......Page 121 Command-based Interface......Page 122 Example: CPU Pipeline......Page 124 Example: BCU......Page 126 Example: USB......Page 128 Separating Data and Control......Page 130 General Connectivity......Page 131 Summary......Page 133 Chapter 9: Complexity at the Chip Level......Page 135 From Command to Transaction Interfaces......Page 138 JPEG Example......Page 139 USB Example......Page 140 Virtual Platforms and Software Development......Page 141 Connectivity and Bandwidth......Page 142 Transactions and Complexity......Page 143 Limits to Chip Level Verification......Page 145 Sub-systems and SoC Design......Page 146 Summary......Page 149 The Challenge......Page 150 Current High Level Synthesis Tools......Page 151 Closing the Abstraction Gap......Page 156 SystemC......Page 157 SystemVerilog as a High Level Design Language......Page 158 Raising the Level of Abstraction of RTL......Page 160 SystemVerilog as a Domain Specific Language......Page 161 SystemVerilog Primitives......Page 162 Proposal......Page 163 Basic Extensions......Page 165 smodule......Page 168 bit_comb......Page 169 state_machine......Page 170 Functions and Tasks......Page 171 Iterative State Loops......Page 172 Fork and Join......Page 176 Summary......Page 178 There is No Substitute for Good Code......Page 179 Chapter 12: The Future of Design......Page 181 Function Does Not Scale......Page 182 Small is Beautiful – and Tractable......Page 185 Automation and Scaling......Page 186 Verification......Page 187 Visualization......Page 188 Drivers of the Solution......Page 189 Summary......Page 190 General......Page 191 Interfaces......Page 192 Partitioning......Page 193 Sign-/Zero-extension......Page 194 Mixed Unsigned/Signed Expression......Page 195 Signed part-select / concatenation......Page 196 Cluster Datapath Portions......Page 197 Component Instantiation......Page 198 Complementing an Operand......Page 199 Simple Hierarchical State Machine in synthesizable SystemVerilog......Page 200 C Version......Page 203 Final RTL Version......Page 205 DCT Using Proposed SystemVerilog Extensions......Page 211 Overview......Page 215 Proposal – New Module Type......Page 216 Sequential and Combinational Processes......Page 217 Operators......Page 218 $clock......Page 219 $reset......Page 220 Tasks......Page 222 Functions......Page 223 Limitations:......Page 224 Reference for Examples......Page 225 Example 1 – Extended data types in processes......Page 226 Example 3 - A slightly more complex example......Page 227 Translation Example – Simple State Machine......Page 228 Interfaces......Page 231 Parameters of Type Type......Page 232 FIFOs......Page 233 push_front()......Page 234 push_back()......Page 235 References......Page 239 Index......Page 241