System Firmware : An Essential Guide to Open Source and Embedded Solutions

Find the right bootloader solution or combination of firmware required to boot a platform considering its security, product features, and optimized boot solutions. This book covers system boot firmware, focusing on real-world firmware migration from closed source to open source adaptation. The book provides an architectural overview of popular boot firmware. This includes both closed sourced and/or open source in nature, such as Unified Extensible Firmware Interface (UEFI), coreboot, and Slim Bootloader and their applicable market segments based on product development and deployment requirements. Traditional system firmware is often complex and closed sourced whereas modern firmware is still a kind of hybrid between closed and open source. But what might a future firmware model look like? The most simplistic boot firmware solution uses open source firmware development. This book helps you decide how to choose the right boot firmware for your products and develop your own boot firmware using open source. Coverage includes: Why open source firmware is used over closed source The pros and cons of closed and open source firmware A hybrid work model: for faster bring-up activity using closed source, binary integrated with open source firmware What You Will Learn Understand the architecture of standard and popular boot firmware Pick the correct bootloader for your required target hardware Design a hybrid workflow model for the latest chipset platform Understand popular payload architectures and offerings for embedded systems Select the right payload for your bootloader solution to boot to the operating system Optimize the system firmware boot time based on your target hardware requirement Know the product development cycle using open source firmware development Who This Book Is For Embedded firmware and software engineers migrating the product development from closed source firmware to open source firmware for product adaptation needs as well as engineers working for open source firmware development. A secondary audience includes engineers working on various bootloaders such as open source firmware, UEFI, and Slim Bootloader development, as well as undergraduate and graduate students working on developing firmware skill sets. Table of Contents About the Authors About the Technical Reviewers Foreword by Jonathan Zhang Preface Acknowledgments Introduction Chapter 1: Introduction Lack of Open System Design Misinterpretation of Firmware Definition Attract the Talent The Importance of Programming Knowledge Specialized Education The Origin of Firmware Firmware Evolution Infancy (Early 1970 to Mid-1980s) Childhood (Mid-1980s to Late 1990s) The POST (Power-On Self-Test) User Interface BIOS Services BIOS Interrupt Call Plug and Play BIOS (PnP BIOS) Bootstrap Loader Adolescence (2000 to 2015) Open Firmware UEFI Security ACPI Alternative Ecosystem Approach Adulthood (the Modern Era of Firmware Since 2015) Openness Security Hybrid Firmware Architecture Modern System Programming Language Distinction Between Firmware and Software Introduction of Non-Host Firmware Introduction to Device Firmware Open Source vs. Closed Source Summary Chapter 2: Knowing Your Hardware Computer Architecture Instruction Set Architecture CISC and RISC Microarchitecture 8086 Microarchitecture Bus Interface Unit Execution Unit System Architecture Memory Unit I/O Devices Buses CPU Internals Internals of x86 Processors Registers General Purpose Registers (GPR) Special Purpose Registers (SPR) Segment Registers Status and Control Register Instruction Pointer Registers (IP) Control Registers (CR) Vector Registers Model-Specific Registers (MSR) Memory Type Range Registers (MTRRs) Processor Modes Real Mode Interrupt Vector Table Protected Mode Global Descriptor Table Register (GDTR) Local Descriptor Table Register (LDTR) Interrupt Descriptor Table Register (IDTR) Task Register (TR) System Management Mode (SMM) Virtual 8086 Mode Interrupt Programmable Interrupt Controller Advanced Programmable Interrupt Controller Local Advanced Programmable Interrupt Controller I/O Advanced Programmable Interrupt Controller Message Signaled Interrupt Timers Real-Time Clock System Timer Internals of ARM Processors Instruction Sets Processor Modes Exception Levels Registers Program Status Registers Program Counter Registers Processor Architecture Caches Memory Management Unit System Memory Map Legacy Address Range Conventional Memory Range Upper Memory Range Main Memory Address Range PCI Memory Address Range Main Memory Upper Address Range Top of Upper Usable DRAM Memory Remapping Top of Memory Upper PCI Memory Address Range Bus Architecture Industry Standard Architecture (ISA) Bus Extended Industry Standard Architecture (EISA) Bus Peripheral Component Interconnect (PCI) Bus Peripheral Component Interconnect Express (PCIe) Bus Serial AT attachment (SATA) Bus Universal Serial Bus (USB) ARM Advanced Microcontroller Bus Architecture (AMBA) AMBA High-Speed Bus (AHB) AMBA Peripheral Bus (APB) Platform Runtime Power Management ACPI Hardware/Registers Fixed Hardware/Register Generic Hardware/Register ACPI System Description Tables ACPI Platform Firmware ACPI Source Language Overview System Power States Summary Chapter 3: Understanding the BIOS and Minimalistic Design What Is the BIOS? Working Principle of BIOS Where Does the BIOS Reside? BIOS Work Model Types of BIOS Designing a Minimalistic Bootloader Minimalistic Bootloader Design on x86 Platform SPI Flash Layout Pre-Reset Flow Minimal Bootloader Flow (Post Reset) Host CPU at Reset Vector Processor Operational Modes and Mode Switching Pre-Memory Initialization NEM (Non-Evict Mode) Early Chipset Initialization Memory Initialization Post Memory Initialization Memory Test Shadowing Tear Down the CAR MP (Multi-Processor) Initialization Startup Inter-Processor Interrupt (SIPI) BSP Initialization Sequence AP Initialization Sequence Late Chipset Initialization GPIO Programming Interrupt Configuration PCI Enumeration Graphics Initialization Boot Media Initialization Booting to the OS OS Handoff Lists e820 Table Programmable Interrupt Routing Table Multiprocessor Specification Table System Management BIOS Table Creation of ACPI Tables BIOS Runtime Services BIOS AL Services Minimalistic Bootloader Design on the ARM Platform Trusted Firmware Power State Coordination Interface SMC Calling Convention TF Architecture Firmware Configuration Firmware Image Package (FIP) Firmware Authentication Boot Loader Stages Summary Chapter 4: System Firmware Architecture UEFI Architecture UEFI Specification Objects UEFI Images EFI System Table Protocols Globally Unique Identifier (GUIDs) Handle Database Events UEFI Driver Model EFI Driver Binding Protocol Driver Connection Process Device Paths EFI Byte Code Platform Initialization Specification Security Phase Pre-EFI Initialization Phase PEI Foundation PEI Services PEI Dispatcher Pre-EFI Initialization Modules PEIM-to-PEIM Interfaces (PPIs) Firmware Volumes (FVs) Hand-Off Blocks (HOBs) Dispatch of the DXE Foundation Driver Execution Environment Phase DXE Foundation DXE Dispatcher DXE Drivers DXE Architectural Protocols Boot Device Selection Phase Transient System Load Phase Runtime Phase After Life Phase coreboot Architecture Platform Initialization Bootblock Verstage Romstage CBMEM In-Memory Database (IMD) Relocatable Modules (rmodules) Postcar Ramstage Boot State Machine Device tree Payload Runtime Services Source Tree Structure SoC Code Structure Common Code Architecture Mainboard Code Structure Dynamic Generation of the ACPI Table Baseboard and Variant Structure Proprietary Silicon Initialization Binary Slim Bootloader Architecture Boot Stages Stage 1 Stage 1A Stage 1B Stage 2 Payload Payload Interface Built-in Payloads External Payloads Boot Flow Normal Boot Mode S3 and S4 Boot Modes Firmware Update Boot Mode Flash Layout Flash Map Redundant Partitions Board Configuration Static Configuration Dynamic Configuration Source Tree Structure Base Tools Bootloader Common and Core Package Silicon Package Platform Package Payload Package Summary Chapter 5: Hybrid Firmware Architecture Understanding the System Firmware Development Model Generic Platform Initialization (PI) Understanding the System Firmware Supply Chain Platform Initialization Wrapper Layer Boot Firmware Spectrum of Open and Closed Source System Firmware Current Industry Trends with Hybrid Firmware Challenges Seen by Silicon Vendors with Open Sourcing Datasheet Dependency Third-Party IP Restrictions Silicon Reference Code Development Without Compatibility Early Platform Enabling with Non-PRQ’ed Silicon Distinguished Product Features Limited Customer Demand Closed-Source Mindset Documentation Is an Afterthought Importance of a Specific System Firmware Architecture Challenges Faced by the Open Community with Closed Sourcing Security Platform Enabling Motivation Is Lagging Hard to Debug Ungoverned Growth for Closed Source Blobs Hybrid Firmware Architecture Ground Rules Firmware Development Using Hybrid Firmware Architecture Conventional Closed Source Firmware in the Hybrid Work Model Overview of AMD’s AGESA and Its Work Model Overview of Qualcomm’s QTISECLIB and a Working Model on TF-A Overview of Intel Firmware Support Package Application of Hybrid Firmware Architecture Summary Chapter 6: Payload Depthcharge Depthcharge Architecture Bootloader Libpayload Verified Boot Kernel Verification Handling Chrome OS Boot Modes Verified Mode Recovery Mode Developer Mode Legacy Mode Depthcharge Shell Depthcharge Boot Flow Depthcharge Code Structure Value-Added Services EC Software Sync PD Firmware Update UEFI Payload UEFI Payload Architecture UEFI Payload Flash Layout Interface Between Bootloader and UEFI Payload Bootloader BlParseLib UEFI Payload Boot Flow UEFI Payload Code Structure Value-Added Services LinuxBoot LinuxBoot Architecture Bootloader Linux Kernel Initramfs (Initial RAM Filesystem) u-root SystemBoot fbnetboot localboot LinuxBoot Boot Flow LinuxBoot Code Structure Value-Added Services The u-root Shell Universal Payload Layer (UPL) Universal Payload Image Format Universal Payload Image Information Section Universal Payload Support Extra Image Section Universal Payload Interface Implementation of Universal Payload Layer Summary Untitled Untitled Chapter 7: Case Studies Reduce FW Booting Time Using Multi-Threaded Environment coreboot Bootstrap Processor Application Processor Multithreading ChromeOS Crosh Depthcharge Goal and Motivation Implementation Schema Setting Up the Board Boot Time Measurement with existing System Firmware Design Detailed Implementation Changes in Boot Firmware - coreboot Changes in Payload - Depthcharge Final Boot-Time Measurement Firmware Boot Time Optimization for Capsule Update Firmware Boot Time Optimization Conclusion Supporting New CPU Architecture Migration with UEFI Goal and Motivation Implementation Schema Setting Up the Code Base Detailed Implementation Details on the SEC Phase Details on the DXE Phase Details on BDS, TSL, and RT Phases Porting a New CPU Architecture (Elixir) Conclusion Reducing the System Firmware Boundary with LinuxBoot Goal and Motivation Implementation Schema Setting Up the Board Detailed Implementation LinuxBoot Conclusion Adopting a Hybrid Firmware Development Model Goal and Motivation Implementation Schema Setting Up the Board Detailed Implementation Hybrid Firmware Development Model Conclusion Summary Appendix A Appendix B Glossary Reference Websites References for the Chapter 1 Books Conferences, Journals, and Papers Specifications and Guidelines Websites References for Chapter 5 Index