Spintronics-based Computing

This book provides a comprehensive introduction to spintronics-based computing for the next generation of ultra-low power/highly reliable logic, which is widely considered a promising candidate to replace conventional, pure CMOS-based logic. It will cover aspects from device to system-level, including magnetic memory cells, device modeling, hybrid circuit structure, design methodology, CAD tools, and technological integration methods. This book is accessible to a variety of readers and little or no background in magnetism and spin electronics are required to understand its content. The multidisciplinary team of expert authors from circuits, devices, computer architecture, CAD and system design reveal to readers the potential of spintronics nanodevices to reduce power consumption, improve reliability and enable new functionality. Foreword 6 Contents 8 About theEditors 10 Current-Induced Magnetic Switching for High-Performance Computing 11 1 Introduction 11 2 Current-Induced Magnetic Switching Spintronic Devices 13 2.1 Perpendicular Magnetic Anisotropy Spin Transfer Torque Magnetic Tunnel Junction (PMA STT MTJ) 13 2.2 Racetrack Memory 20 3 Current-Induced Magnetic Switching Based Hybrid Spintronics/CMOS Circuits for High-Performance Computing 26 3.1 Sensing Circuit 26 3.2 Writing Circuit 30 3.3 Magnetic Full Adder 37 3.3.1 1-Bit MFA Based on PMA STT MTJ 37 3.4 Multi-Bit MFA Based on Racetrack Memory 43 3.5 Content Addressable Memory (CAM) Based on Racetrack Memory 48 4 Conclusions and Perspectives 55 References 57 Electric Control of Magnetic Devices for Spintronic Computing 62 1 Introduction 62 2 Electric Field Control of Ferromagnetism in Dilute Magnetic Semiconductors for Novel SpinFETs 64 2.1 Dilute Magnetic Semiconductors with Electric Field Controlled Ferromagnetism 64 2.2 DMS-Based Nonvolatile Transpinor for Spintronic Computing 67 2.2.1 SpinFET as a Promising Candidate for Beyond CMOS Technology 67 2.2.2 DMS-Based SpinFET: Nonvolatile Transpinor 70 3 Voltage Control of Magnetic Anisotropy in Metallic Spintronic Devices 74 3.1 Voltage-Controlled Magnetism: Impact on Memory and Logic 75 3.2 Voltage-Controlled Magnetic Interface Anisotropy 76 3.3 Voltage-Induced Switching of Magnetic Memory Bits 79 3.4 Temperature Dependence of the VCMA Effect 83 3.5 Circuit Implementation of VCMA-Controlled Memory 86 3.6 Scalability of VCMA-Based Magnetoelectric RAM 89 4 Electric Field Controlled Magnetism in Metallic Films Beyond VCMA 92 4.1 Electric Field Controlled Phase Transition in Thin Metallic Films 92 4.2 An Example: Electric Field-Controlled Curie Temperature 94 5 Spin-Orbitronic Devices 95 5.1 Current-Induced Magnetization Switching in Topological Insulators 98 5.2 SOT-Induced Zero-Field Magnetization Switching in Perpendicular Devices 100 5.3 Spin Hall Effect Clocking of Nanomagnetic Logic Without a Magnetic Field 103 6 Applications and Perspectives on Spintronic Computation 105 6.1 Nonvolatile Circuits with Hybrid CMOS and Spintronic Memory 105 6.2 Spin Wave Logic 108 6.3 Electric-Field-Induced Spin Wave Generation Using Multiferroic Magnetoelectric Cells 111 6.4 Spintronics for Special Task Data Processing 114 References 115 Advanced Perpendicular STT-MRAM Technologies for Power Reduction of High-performance Processors 122 1 Introduction 122 2 Fundamentals and Development of Advanced Perpendicular STT-MRAM 123 2.1 Features of Existing Memories and MRAM ́s Target in the Memory Hierarchy 123 2.2 Basic Structure of the MTJ Storage Element 124 2.3 Data Reading and Writing Methods of MRAM 125 2.4 Structure of a Unit Cell of the STT-MRAM 125 2.5 Key Features to Outperform Conventional Memories 125 2.6 Perpendicular Magnetization MTJ for Reduction of the Write Current 126 2.7 Trend of the Switching Current of p-MTJ 128 2.8 Reduction of Energy Consumption of a Mobile Processor by Nonvolatile Cache Memory 130 3 High-Performance and Low-Power Circuit Designs Based on Advanced STT-MRAM 134 3.1 Combination of MRAM and SRAM 134 3.2 DRAM-MRAM Hybrid Memory Design 136 3.3 2T-2MTJ Dual Cell Based Memory Design 142 3.3.1 Current-Integral Sensing Circuit Design of STT-MRAM 144 3.3.2 Dual Cell Topology for Fast Read Operation 146 3.3.3 Memory Array Architecture with Two-Level Hierarchical Bitline Structure 148 3.3.4 1Mb MRAM Design and Measurement Results of Test Chip 149 References 151 Beyond STT-MRAM, Spin Orbit Torque RAM SOT-MRAM for High Speed and High Reliability Applications 153 1 Introduction 153 2 MTJs Written by Spin Orbit Torque 154 3 Applications of SOT-RAM 156 3.1 Introduction in the Memory Hierarchy of Processors 156 3.2 Non-volatile Flip-Flops, Normally-Off/Instant-On Computing and Memory-in-Logic 157 4 Design Tools and Environment for the Design of Hybrid CMOS/SOT-RAM Components 158 4.1 Compact Electrical Model of SOT-MTJ 158 4.2 Ultra-fast SOT-MRAM Based Non-volatile Flip-Flop 159 4.3 System Level Integration 160 5 Conclusion 162 References 163 Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture 166 1 Introduction 166 2 Design Example of NV-LIM-Based FPGA 169 3 Design Example of NV-LIM-Based TCAM 174 4 Design Example of Nonvolatile Random-Access Logic LSI 179 References 183 Logic Circuits Design Based on MRAM: From Single to Multi-States Cells Storage 185 1 Introduction 185 2 MRAM 188 2.1 Field-Induced Magnetic Switching (FIMS) 189 2.2 Thermally-Assisted Switching (TAS) 190 2.3 Current-Induced Magnetic Switching (CIMS) 190 2.4 Trends in Evolution of MTJ Parameters 190 3 Hybrid MTJ/CMOS Logic Circuits 192 3.1 Applications in Processor Domain 192 3.2 Programmable Logic 197 3.3 Logic-in-Memory 199 3.4 Multi Bit MRAM Cells 200 3.5 Emerging MRAM Devices 201 4 Conclusions 202 References 202 Statistical Reliability/Energy Characterization inSTT-RAM Cell Designs 207 1 Introduction 207 2 Preliminary 209 2.1 STT-RAM Basics 209 2.2 Process Variations andProgramming Uncertainty ofSTT-RAM 209 2.2.1 Process Variations-Persistent Errors 209 2.2.2 Thermal Fluctuation-Non-persistent Errors 210 3 PS3-RAM Method 210 3.1 Sensitivity Analysis onMTJ Switching 211 3.1.1 Sensitivity Analysis onVariations 211 3.2 Write Current Distribution Recovery 216 3.3 Statistical Thermal Analysis 219 4 Application 1: Write Reliability Analysis 219 4.1 Reliability Analysis ofSTT-RAM Cells 219 4.2 Array Level Analysis andDesign Optimization 221 5 Application 2: Write Energy Analysis 224 5.1 Write Energy Without Variations 224 5.2 PS3-RAM forStatistical Write Energy 226 6 Computation Complexity Evaluation 228 7 Conclusion 228 Appendix 229 Sensitivity Analysis Model Deduction 229 Analytic Results Summary 231 Validation ofAnalytic Results 231 References 235 Synchronized Spin Torque Nano-Oscillators: From Theory to Applications 237 1 Introduction 237 1.1 Spin Dependent Transport 237 1.2 Spin Transfer Torque 239 2 Modeling the Dynamic Behavior of STNOs 240 3 Electrically Coupled STNOs 241 3.1 Magnetic vs. Electrical Synchronization 241 3.2 Synchronization Dynamics 242 3.3 STNO Array as an Oscillatory Neurocomputer 243 4 STNO Geometry and Oscillations 244 4.1 Harmonicity and Signal Strength 245 4.2 Dual Barrier MTJ 246 5 Application: Pattern Recognition 247 6 Application: Radio Frequency Circuits 251 7 Conclusions 253 Appendix 254 References 254 Index 257 Front Matter....Pages i-ix Current-Induced Magnetic Switching for High-Performance Computing....Pages 1-51 Electric Control of Magnetic Devices for Spintronic Computing....Pages 53-112 Advanced Perpendicular STT-MRAM Technologies for Power Reduction of High-performance Processors....Pages 113-143 Beyond STT-MRAM, Spin Orbit Torque RAM SOT-MRAM for High Speed and High Reliability Applications....Pages 145-157 Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture....Pages 159-177 Logic Circuits Design Based on MRAM: From Single to Multi-States Cells Storage....Pages 179-200 Statistical Reliability/Energy Characterization in STT-RAM Cell Designs....Pages 201-230 Synchronized Spin Torque Nano-Oscillators: From Theory to Applications....Pages 231-250 Back Matter....Pages 251-253