SOC Design Methodologies : IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC’01) December 3–5, 2001, Montpellier, France

The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered. The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention. Front Matter....Pages i-1 Two ASIC for Low and Middle Levels of Real Time Image Processing....Pages 3-14 64 × 64 Pixels General Purpose Digital Vision Chip....Pages 15-26 A vision system on chip for industrial control....Pages 27-38 Fast Recursive Implementation of the Gaussian Filter....Pages 39-49 A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals....Pages 51-62 Dynamically Reconfigurable Architectures for Digital Signal Processing Applications....Pages 63-74 Reconfigurable Architecture Using High Speed FPGA....Pages 75-86 Design Technology for Systems-on-Chip....Pages 87-96 Distributed Collaborative Design over Cave2 Framework....Pages 97-108 High Performance Java Hardware Engine and Software Kernel for Embedded Systems....Pages 109-120 An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures....Pages 121-132 Interconnect Capacitance Modelling in a VDSM CMOS Technology....Pages 133-144 Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design....Pages 145-156 An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms....Pages 157-168 Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 μ m Bulk and Silicon-On-Insulator CMOS Technologies....Pages 169-180 A Standardized Co-simulation Backbone....Pages 181-192 Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory....Pages 193-204 Modeling Power Dynamics for an Embedded DSP Processor Core....Pages 205-216 Power Consumption Model for the DSP OAK Processor....Pages 217-228 Integration of Robustness in the Design of a Cell....Pages 229-239 Impact of Technology Spreading on MEMS design Robustness....Pages 241-251 A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation....Pages 253-264 Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder....Pages 265-276 Low-Voltage Embedded-RAM Technology: Present and Future....Pages 277-288 Low-Voltage 0.25 μm CMOS Improved Power Adaptive Issue Queue For Embedded Microprocessors....Pages 289-300 Gate sizing for low power design....Pages 301-312 Modeling and design of asynchronous priority arbiters for on-chip communication systems....Pages 313-324 Feasible delay bound definition....Pages 325-335 CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors....Pages 337-347 A VHDL-AMS Case Study....Pages 349-360 Speeding Up Verification of RTL Designs by Computing One-to-One Abstractions with Reduced Signal Widths....Pages 361-374 Functional Test Generation Using Constraint Logic Programming....Pages 375-387 An Industrial Approach to Core-Based System Chip Testing....Pages 389-400 Power-constrained Test Scheduling for SoCs under a “no session” scheme....Pages 401-412 Random Adjacent Sequences....Pages 413-424 On-chip generator of a saw-tooth test stimulus for ADC BIST....Pages 425-436 Built-in test of analog non-linear circuits in a SOC environment....Pages 437-448 Design of a Fast CMOS APS Imager for High Speed Laser Detections....Pages 449-460 Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing....Pages 461-472 Back Matter....Pages 473-477 The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs et Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered. The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention The current trend towards the realization of complex Systems On Chips (SOCs) required the combined efforts and attention of experts in a wide range of areas including embedded hardware/software systems, specific IP cores, reconfigurable architectures, signal and image processing architectures, low power design techniques, design methods and CAD tools, test and verification, modeling, timing issues. Thus the papers presented herein address a wide range of SOC design topics. SOC Design Methodologies comprises a selection of the best papers presented at VLSI-SOC'01, the Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip, which was sponsored by the International Federation for Information Processing (IFIP) Technical Committee 10 / Working Group 10.5, and held in Montpellier, France in December 2001. This volume is essential reading for researchers working on microelectronics system integration, design, and CAD of integrated circuits and systems on chips