Semiconductor Advanced Packaging

The book focuses on the design, materials, process, fabrication, and reliability of advanced semiconductor packaging components and systems. Both principles and engineering practice have been addressed, with more weight placed on engineering practice. This is achieved by providing in-depth study on a number of major topics such as system-in-package, fan-in wafer/panel-level chip-scale packages, fan-out wafer/panel-level packaging, 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, chiplets packaging, chip-to-wafer bonding, wafer-to-wafer bonding, hybrid bonding, and dielectric materials for high speed and frequency. The book can benefit researchers, engineers, and graduate students in fields of electrical engineering, mechanical engineering, materials sciences, and industry engineering, etc. Preface Acknowledgments Contents About the Author 1 Advanced Packaging 1.1 Introduction 1.2 Semiconductor Applications 1.3 System-Technology Drivers 1.3.1 AI 1.3.2 5G 1.4 Advanced Packaging 1.4.1 Kinds of Advanced Packaging 1.4.2 Groups of Advanced Packaging 1.5 2D Fan-Out (Chip-First) IC Integration 1.6 2D Flip Chip IC Integration 1.7 PoP, SiP, and Heterogeneous Integration 1.8 2D Fan-Out (Chip-Last) IC Integration 1.9 2.1D Flip Chip IC Integration 1.10 2.1D Flip Chip IC Integration with Bridges 1.11 2.1D Fan-Out IC Integration with Bridges 1.12 2.3D Fan-Out (Chip-First) IC Integration 1.13 2.3D Flip Chip IC Integration 1.14 2.3D Fan-Out (Chip-Last) IC Integration 1.15 2.5D (C4 Bump) IC Integration 1.16 2.5D (C2 Bump) IC Integration 1.17 μBump 3D IC Integration 1.18 μBump Chiplets 3D IC Integration 1.19 Bumpless 3D IC Integration 1.20 Bumpless Chiplets 3D IC Integration 1.21 Summary and Recommendation References 2 System-in-Package (SiP) 2.1 Introduction 2.2 SoC (System-on-Chip) 2.3 System-in-Package (SiP) 2.4 Intention of SiP 2.5 Actual Applications of SiP 2.6 SiP Examples 2.7 SMT 2.7.1 PCB 2.7.2 SMDs 2.7.3 Solder Paste 2.7.4 Stencil Printing Solder Paste and AOI 2.7.5 Pick and Place of SMDs 2.7.6 AOI of SMDs on PCB 2.7.7 SMT Solder Reflow 2.7.8 AOI and X-Ray Inspection for Defects 2.7.9 Re-Work 2.7.10 Summary and Recommendation 2.8 Flip Chip Technology 2.8.1 Wafer Bumping by Stencil Printing 2.8.2 C4 (Controlled Collapse Chip Connection) Wafer Bumping 2.8.3 C2 (Chip Connection) Wafer Bumping 2.8.4 Flip Chip Assembly—Mass Reflow of C4 or C2 Bumps (CUF) 2.8.5 Underfill for Reliability 2.8.6 Flip Chip Assembly—TCB with Low-Force of C4 or C2 Bumps (CUF) 2.8.7 Flip Chip Assembly—TCB with High-Force of C2 Bumps (NCP) 2.8.8 Flip Chip Assembly—TCB with High-Force of C2 Bumps (NCF) 2.8.9 An Advanced Flip Chip Assembly—LPC TCB of C2 Bumps 2.8.10 Summary and Recommendation References 3 Fan-In Wafer/Panel-Level Chip-Scale Packages 3.1 Introduction 3.2 Fan-In Wafer-Level Chip-Scale Packages (WLCSPs) 3.2.1 The Structure 3.2.2 WLCSP Key Process Steps 3.2.3 PCB Assembly of WLCSP 3.2.4 Thermal Simulation of the WLCSP PCB Assembly 3.2.5 Summary and Recommendation 3.3 Fan-In Panel-Level Chip-Scale Packages (PLCSPs) 3.3.1 Test Chip 3.3.2 Test Package 3.3.3 PLCSP Process Flow 3.3.4 PCB Assembly of the PLCSP 3.3.5 Drop Test of PLCSP PCB Assembly 3.3.6 Thermal Cycling Test of PLCSP PCB Assembly 3.3.7 Thermal Cycling Simulation of the PLCSP PCB Assembly 3.3.8 Summary and Recommendation 3.4 Six-Side Molded Wafer-Level Chip-Scale Packages 3.4.1 eWLCSP by Statschippac 3.4.2 WLCSP by UTAC 3.4.3 mWLCSP by SPIL 3.4.4 WLCSP by Huatian 3.4.5 mWLCSP by SPIL and MediaTek 3.4.6 Summary and Recommendation 3.5 Six-Side Molded Panel-Level Chip-Scale Packages 3.5.1 The 6-Side Molded PLCSP Structure 3.5.2 Cutting and EMC Molding of Wafer from the Front-Side 3.5.3 Backgrinding and Wafer Backside Molding 3.5.4 Plasma Etching and Dicing 3.5.5 Test PCB 3.5.6 SMT Assembly of the 6-Side Molded PLCSP on PCB 3.5.7 Thermal Cycling Test of the 6-Side Molded PLCSP 3.5.8 Thermal Cycling Simulation of the 6-Side Molded PLCSP PCB Assembly 3.5.9 Summary and Recommendation References 4 Fan-Out Wafer/Panel-Level Packaging 4.1 Introduction 4.2 Fan-Out (Chip-First and Face-Down) Wafer-Level Packaging (FOWLP) 4.2.1 Test Chips 4.2.2 Test Package 4.2.3 Conventional Chip-First (Face-Down) Wafer Process 4.2.4 New Process for Heterogeneous Integration Package 4.2.5 Dry-Film EMC Lamination 4.2.6 Temporary Bonding Another Glass Carrier 4.2.7 RDLs 4.2.8 Solder Ball Mounting 4.2.9 Final De-Bonding 4.2.10 PCB Assembly 4.2.11 Reliability (Drop Test) of the Heterogeneous Integration 4.2.12 Summary and Recommendation 4.3 Fan-Out (Chip-First and Face-Down) Panel-Level Packaging (FOPLP) 4.3.1 Heterogeneous Integration of Test Package 4.3.2 A New Uni-SIP Process 4.3.3 Dry-Film Lamination of ECM-Panel 4.3.4 Lamination of Uni-SIP Structure 4.3.5 Lamination of the New ABF, Laser Drilling, and De-Smearing 4.3.6 LDI and PCB Cu-Plating 4.3.7 Summary and Recommendation 4.4 Fan-Out (Chip-First and Face-Up) Wafer-Level Packaging 4.4.1 Test Chip 4.4.2 Process Flow 4.5 Fan-Out (Chip-First and Face-up) Panel-Level Packaging 4.5.1 The Structure 4.5.2 Process Flow 4.6 Fan-Out (Chip-Last or RDL-First) Wafer-Level Packaging 4.6.1 IME’s RDL-First FOWLP 4.6.2 Test Structure 4.6.3 RDL-First Key Process Steps 4.6.4 RDL-First FOWLP on PCB Assembly 4.7 Fan-Out (Chip-Last or RDL-First) Panel-Level Packaging 4.7.1 Test Chips 4.7.2 Test Package 4.7.3 RDL-First Panel-Level Packaging for Heterogeneous Integration 4.7.4 Fabrication of Redistribution-Layer Substrate 4.7.5 Wafer Bumping 4.7.6 Chip-to-Substrate Bonding 4.7.7 Underfilling and EMC Molding 4.7.8 Panel/Strip Transfer 4.7.9 Solder Resist Opening and Surface Finishing 4.7.10 Solder Ball Mounting, Debonding, and Strip Dicing 4.7.11 PCB Assembly of the RDL-First Panel-Level Package 4.7.12 Drop Test Results and Failure Analysis 4.7.13 Thermal-Cycling Test Results and Failure Analysis 4.7.14 Thermal-Cycling Simulation 4.7.15 Summary and Recommendation 4.8 Fan-Out Panel-Level Packaging of Mini-LED RGB Display 4.8.1 Test Mini—LEDS 4.8.2 Test Mini-LED RGB Display SMD Package 4.8.3 RDL and Mini-LED RGB SMD Fabrication 4.8.4 PCB Assembly 4.8.5 Drop Test 4.8.6 Thermal Cycling Simulation 4.8.7 Summary and Recommendation References 5 2D, 2.1D, and 2.3D IC Integration 5.1 Introduction 5.2 2D IC Integration—Wire Bonging 5.3 2D IC Integration—Flip Chip 5.4 2D IC Integration—Wire Bonging and Flip Chip 5.5 RDLs 5.5.1 Organic RDLs 5.5.2 Inorganic RDLs 5.5.3 Hybrid RDLs 5.6 2D IC Integration—Fan-Out (Chip-First) 5.6.1 HTC’s Desire 606 W 5.6.2 Heterogeneous Integration of 4 Chips 5.7 2D IC Integration—Fan-Out (Chip-Last) 5.7.1 IME’s Fan-Out with Chip-Last 5.7.2 Amkor’s SWIFT 5.7.3 Amkor’s SLIM 5.7.4 SPIL’s Fan-Out on Hybrid RDLs 5.7.5 Unimicron’s Fan-Out with Chip-Last 5.8 2.1D IC Integration 5.8.1 Shinko’s I-THOP 5.8.2 Hitachi’s 2.1D Organic Interposer 5.8.3 ASE’s 2.1D Organic Interposer 5.8.4 SPIL’s 2.1D Organic Interposer 5.8.5 JCET’s UFOS 5.8.6 Intel’s EMIB 5.8.7 Applied Materials’ Bridge 5.8.8 TSMC’S LSI 5.9 2.3D IC Integration 5.10 2.3D IC Integration with SAP/PCB Method 5.10.1 Shinko’s Coreless Organic Interposer 5.10.2 Cisco’s Organic Interposer 5.11 2.3D IC Integration with Fan-Out (Chip-First) Method 5.11.1 Statschippac’s 2.3D eWLB 5.11.2 Mediatek’s Fan-Out (Chip-First) 5.11.3 ASE’s FOCoS (Chip-First) 5.11.4 TSMC’s InFOOS and InFOMS 5.12 2.3D IC Integration with Fan-Out (Chip-Last) Method 5.12.1 SPIL’S NTI 5.12.2 Samsung’s Si-Less RDL Interposer 5.12.3 ASE’s FOCoS (Chip-Last) 5.12.4 TSMC’s Multilayer RDL Interposer 5.12.5 Shinko’s 2.3D Organic Interposer 5.12.6 Unimicron’s 2.3D RDL-Interposer 5.13 Summary and Recommendation References 6 2.5D IC Integration 6.1 Introduction 6.2 Leti’s SoW (the Origin of 2.5D IC Integration) 6.3 IME’s 2.5D IC Integration 6.3.1 3D Nonlinear Local and Global Analysis of 2.5D IC Integration 6.3.2 2.5D IC Integration for Electrical and Fluidic Interconnects 6.3.3 Double Stacked Passive TSV-Interposers 6.3.4 TSV-Interposer Used as Stress (Reliability) Buffer 6.4 HKUST’s TSV-Interposer with Chips on Both Sides 6.5 ITRI’s 2.5D IC Integration 6.5.1 Thermal Management of TSV-Interposer with Chips on Both Sides 6.5.2 TSV-Interposer with Embedded Fluidic Microchannels for LEDs 6.5.3 TSV-Interposer with SoCs and Memory Cube 6.5.4 Semi-embedded TSV-Interposer 6.5.5 TSV-Interposer with Double-Sided Chip Attachments 6.5.6 TSV-Interposer with Chips on Both Sides 6.5.7 Through-Silicon Hole-Interposer (TSH-Interposer) 6.6 TSMC’s CoWoS 6.7 Xilinx/TSMC’s 2.5D IC Integration 6.8 Altera/TSMC’s 2.5D IC Integration 6.9 AMD/UMC’s 2.5D IC Integration 6.10 NVidia/TSMC’s 2.5D IC Integration 6.11 TSMC’s CoWoS Roadmap 6.12 Recent Advances in 2.5D IC Integration 6.12.1 TSMC’s CoWoS with Deep Trench Capacitor (DTC) 6.12.2 IME’s Non-destructive Fault Isolation in 2.5D IC Integration 6.12.3 Fraunhofer’s Photonics Interposer 6.12.4 Dai Nippon/AGC’s Glass Interposer 6.12.5 Fujitsu’s Multilayer Glass Interposer 6.13 Summary and Recommendation References 7 3D IC Integration and 3D IC Packaging 7.1 Introduction 7.2 3D IC Packaging 7.2.1 3D IC Packaging—Memory Stack with Wire Bonding 7.2.2 3D IC Packaging—Face-to-Face Bonding with Wire Bonding to Substrate 7.2.3 3D IC Packaging—Back-to-Back Bonding with Wire Bonding to Substrate 7.2.4 3D IC Packaging—Face-to-Face Bonding with Solder Bump/Ball to Substrate 7.2.5 3D IC Packaging—Face-to-Back 7.2.6 3D IC Packaging—Embedded Chip (Face-to-Face) in SiP 7.2.7 3D IC Packaging—PoP with Flip-Chip Technology 7.2.8 3D IC Packaging—PoP with Fan-Out Technology 7.2.9 Summary and Recommendation 7.3 3D IC Integration 7.3.1 3D IC Integration—HBM Specifications 7.3.2 3D IC Integration—HBM Assembly 7.3.3 3D IC Integration—Chip-on-Chip with TSVs 7.3.4 3D IC Integration—Bumpless Hybrid Bonding of Chip-on-Chip with TSVs 7.3.5 3D IC Integration—Bumpless Hybrid Bonding of Chip-on-Chip Without TSVs 7.3.6 Summary and Recommendation References 8 Hybrid Bonding 8.1 Introduction 8.2 Cu–Cu TCB 8.2.1 Some Fundamental on Cu–Cu TCB 8.2.2 IBM/RPI’s Cu–Cu TCB 8.3 Cu–Cu TCB at Room Temperature 8.3.1 Some Fundamental on Cu–Cu TCB at Room Temperature 8.3.2 NIMS/AIST/Toshiba/University of Tokyo’s Cu–Cu TCB at Room Temperature 8.4 SiO2–SiO2 TCB 8.4.1 Some Fundamental on SiO2–SiO2 TCB 8.4.2 MIT’s SiO2–SiO2 TCB 8.4.3 Leti/Freescale/STMicroelectronics’ SiO2–SiO2 TCB 8.5 Low Temperature DBI 8.5.1 Some Fundamental on Low Temperature DBI 8.5.2 Sony’s CMOS Image Sensors (CIS) with TSVs 8.5.3 Sony’s CIS Without TSV (Hybrid Bonding) 8.6 Recent Developments of Low Temperature Hybrid Bonding 8.6.1 IME’s Thermo-Mechanical Performance of Hybrid Bonding 8.6.2 TSMC’s Hybrid Bonding 8.6.3 IMEC’s Hybrid Bonding 8.6.4 Globalfoundries’ Hybrid Bonding 8.6.5 Mitsubishi’s Hybrid Bonding 8.6.6 Leti’s Hybrid Bonding 8.6.7 Intel’s Hybrid Bonding 8.7 Summary and Recommendation References 9 Chiplet Heterogeneous Integration 9.1 Introduction 9.2 DARPA’s Efforts in Chipet Heterogeneous Integration 9.3 SoC (System-on-Chip) 9.4 Chiplet Heterogeneous Integration 9.5 Advantages and Disadvantages of Chiplet Heterogeneous Integration 9.6 Advanced Packaging for Chiplet Heterogeneous Integration 9.6.1 2D Chiplet Heterogeneous Integration on Organic Substrate 9.6.2 2.1D Chiplet Heterogeneous Integration on Organic Substrate 9.6.3 2.3D Chiplet Heterogeneous Integration on Organic Substrate 9.6.4 2.5D Chiplet Heterogeneous Integration on Silicon Substrate (Passive TSV-Interposer) 9.6.5 3D Chiplet Heterogeneous Integration on Silicon Substrate (Active TSV-Interposer) 9.6.6 Chiplet Heterogeneous Integration on Organic Substrate with Silicon Bridges 9.6.7 PoP Chiplet Heterogeneous Integration 9.6.8 Chiplet Heterogeneous Integration on Fan-Out RDL-Substrate 9.7 AMD’s Chiplet Heterogeneous Integration 9.8 Intel’s Chiplet Heterogeneous Integration 9.9 TSMC’s Chiplet Heterogeneous Integration 9.10 Summary and Recommendation References 10 Low Loss Dielectric Materials 10.1 Introduction 10.2 Why Need Low Dk and Df Dielectric Materials? 10.3 Why Need Low CTE Dielectric Materials? 10.4 NAMICS’s Dk and Df 10.5 Arakawa’s Dk and Df 10.6 DuPont’s Dk and Df 10.7 Hitachi/DuPont MicroSystems’ Dk and Df 10.8 JSR’s Dk and Df 10.9 Toray’s Dk and Df 10.10 Fujitsu’s Dk and Df 10.11 Kayaku’s Dk and Df 10.12 Mitsubishi’s Dk and Df 10.13 TAITO INK’s Dk and Df 10.14 Zhejiang University’s Dk and Df 10.15 Summary and Recommendation References 11 Advanced Packaging Trends 11.1 Introduction 11.2 The Impact of COVID-19 on Semiconductor Industry 11.3 The Impact of COVID-19 on Foundry Industry 11.4 The Impact of COVID-19 on the Semiconductor Customers 11.5 The Impact of COVID-19 on Packaging Industry 11.6 Drivers, Semiconductor, and Advanced Packaging 11.7 Assembly Process for Advanced Packaging 11.7.1 Wire Bonding 11.7.2 SMT 11.7.3 Wafer Bumping for Flip Chip Technology 11.7.4 Flip Chip on Organic Substrates 11.7.5 CoC, CoW, and WoW TCB and Hybrid Bonding 11.8 Fan-Out Chip-First (Face-up), Chip-First (Face-Down), and Chip-Last 11.9 Bridges Versus TSV-Interposer 11.10 SoC Versus Chiplets 11.11 Material Requirement for HS/HF Applications 11.12 Summary and Recommendation References Index