Post-Silicon Validation and Debug

This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs Front Matter ....Pages i-xv Front Matter ....Pages 1-1 Post-Silicon SoC Validation Challenges (Farimah Farahmandi, Prabhat Mishra)....Pages 3-16 Front Matter ....Pages 17-17 SoC Instrumentations: Pre-Silicon Preparation for Post-Silicon Readiness (Sandip Ray)....Pages 19-32 Structural Signal Selection for Post-Silicon Validation (Kanad Basu)....Pages 33-56 Simulation-Based Signal Selection (Debapriya Chatterjee, Valeria Bertacco)....Pages 57-75 Hybrid Signal Selection (Azadeh Davoodi)....Pages 77-85 Post-Silicon Signal Selection Using Machine Learning (Alif Ahmed, Kamran Rahmani, Prabhat Mishra)....Pages 87-107 Front Matter ....Pages 109-109 Observability-Aware Post-Silicon Test Generation (Farimah Farahmandi, Prabhat Mishra)....Pages 111-123 On-Chip Constrained-Random Stimuli Generation (Xiaobing Shi, Nicola Nicolici)....Pages 125-144 Test Generation and Lightweight Checking for Multi-core Memory Consistency (Doowon Lee, Valeria Bertacco)....Pages 145-178 Selection of Post-Silicon Hardware Assertions (Pouya Taatizadeh, Nicola Nicolici)....Pages 179-208 Front Matter ....Pages 209-209 Debug Data Reduction Techniques (Sandeep Chandran, Preeti Ranjan Panda)....Pages 211-229 High-Level Debugging of Post-Silicon Failures (Masahiro Fujita, Qinhao Wang, Yusuke Kimura)....Pages 231-253 Post-Silicon Fault Localization with Satisfiability Solvers (Georg Weissenbacher, Sharad Malik)....Pages 255-273 Coverage Evaluation and Analysis of Post-Silicon Tests with Virtual Prototypes (Kai Cong, Fei Xie)....Pages 275-306 Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis (Farimah Farahmandi, Prabhat Mishra)....Pages 307-321 Front Matter ....Pages 323-323 Network-on-Chip Validation and Debug (Subodha Charles, Prabhat Mishra)....Pages 325-342 Post-Silicon Validation of the IBM POWER8 Processor (Tom Kolan, Hillel Mendelson, Amir Nahir, Vitali Sokhin)....Pages 343-363 Front Matter ....Pages 365-365 SoC Security Versus Post-Silicon Debug Conflict (Yangdi Lyu, Yuanwen Huang, Prabhat Mishra)....Pages 367-384 The Future of Post-Silicon Debug (Farimah Farahmandi, Prabhat Mishra)....Pages 385-390 Back Matter ....Pages 391-394