مشخصات PCI Express M.2، ویرایش ۴.۰، نسخه ۱.۰

1. Introduction to M.2 Specification 1.1. Terms and Definitions 1.2. Targeted Application 1.3. Specification References 2. Mechanical Specification 2.1. Overview 2.2. Card Type Naming Convention 2.3. Card Specifications 2.3.1. Card Form Factors Intended for Connectivity Socket 1 2.3.1.1. Type 2230 Specification 2.3.1.2. Type 1630 Specification 2.3.1.3. Type 3030 Specification 2.3.2. Card Form Factors Intended for WWAN Socket 2 2.3.2.1. Type 3042 Specification 2.3.2.2. Type 2242 Specification 2.3.3. Card Form Factor for SSD Socket 2 and 3 2.3.3.1. Type 2230 Specification 2.3.3.2. Type 2242 Specification 2.3.3.3. Type 2260 Specification 2.3.3.4. Type 2280 Specification 2.3.3.5. Type 22110 Specification 2.3.3.6. Type 25110 Specification 2.3.4. Card PCB Details 2.3.4.1. Mechanical Outline of Card-Edge 2.3.4.2. Add-in Card Keying 2.3.5. Soldered-down Form Factors 2.3.5.1. Type 2226 Specification 2.3.5.2. Type 1216 Specification 2.3.5.3. Type 3026 Specification 2.3.6. Soldered-Down Form Factors for BGA SSDs 2.3.6.1. Type 1113 Specification 2.3.6.2. Type 1620 Specification 2.3.6.3. Type 2024 Specification 2.3.6.4. Type 2228 Specification 2.3.6.5. Type 2828 Specification 2.3.7. RF Connectors 2.3.7.1. Socket 1 and 2 RF Connector Pinout 2.4. System Connector Specifications 2.4.1. Connector Pin Count 2.4.2. Contact Pitch 2.4.3. System Connector Parametric Specifications 2.4.4. Additional Environmental Requirements 2.4.5. Card Insertion 2.4.6. Point of Contact Guideline 2.4.7. Top-side Connection 2.4.7.1. Top-side Connector Physical Dimensions 2.4.7.2. Top-side Connection Total System Length 2.4.7.3. Top-side Connection Stack-up 2.4.7.3.1. Single-sided Add-in Card (Using H2.3 Connector) 2.4.7.3.2. Single-sided Add-in Card (Using H2.5 Connector) 2.4.7.3.3. Double-sided Add-in Card (Using H2.8, H3.2 and H4.2 Connector) 2.4.7.4. Top-side Connector Layout Pattern 2.4.8. Mid-mount Connection (Using M1.8 Connector) 2.4.8.1. Mid-mount Connector Physical Dimensions 2.4.8.2. Mid-mount Connection Total System Length 2.4.8.3. Mid-mount Connection Stack-up 2.4.8.3.1. Single-sided Add-in Card 2.4.8.3.2. Double-sided Add-in Card 2.4.8.4. Mid-mount Connector Layout Pattern 2.4.9. Connector Key Dimension 2.4.9.1. Host Connector Keying 2.5. Module Stand-off 2.5.1. Recommended Main Board Hole 2.5.2. Electrical Ground Path 2.5.3. Thermal Ground Path 2.5.4. Stand-off Guidelines 2.5.4.1. Stand-off Guidelines Option 1 2.5.4.2. Stand-off Guidelines Option 2 2.5.5. Screw Selection Guideline 2.5.5.1. Option 1, Wafer-head Style M3 Screw 2.5.5.2. Option 2, M3 Screw with Tapered Shaft 2.5.5.3. Option 3, Wafer-head Style M2 Screw 2.5.5.4. Option 4, Flat-head Style M3 Screw 2.6. Thermal Guidelines for the M.2 2.6.1. Objective 2.6.2. Introduction to Thermal Management 2.6.2.1. Thermal Design Power Definition 2.6.2.2. Skin Temperature Definition 2.6.2.3. Unpowered M.2 Adapter Temperature 2.6.2.4. System Skin Temperature—Fan-based System 2.6.3. System Skin Temperature—Fanless System 2.6.4. Examples of Dissipation (TDP) Response of Adapters 3. Electrical Specifications 3.1. Connectivity Socket 1 Adapter Interface Signals 3.1.1. Power Sources and Grounds 3.1.2. PCI Express Interface 3.1.3. PCI Express Auxiliary Signals 3.1.3.1. Reference Clock 3.1.3.2. CLKREQ# Signal 3.1.3.2.1. Dynamic Clock Control 3.1.3.3. Clock Request Support Reporting and Enabling 3.1.3.4. PERST# Signal 3.1.3.5. PEWAKE# Signal 3.1.4. Power-up Timing 3.1.4.1. PERST# Power-up Timing 3.1.4.2. REFCLK Power-up Timing 3.1.4.3. CLKREQ# Power-up Timing 3.1.5. USB Interface 3.1.6. DisplayPort Interface 3.1.6.1. DP_HPD 3.1.6.2. DP_MLDIR 3.1.7. SDIO Interface 3.1.8. UART Interface 3.1.8.1. UART_WAKE# 3.1.9. PCM/I2S Interface 3.1.10. I2C Interface 3.1.10.1. ALERT# Signal 3.1.10.2. I2C_DATA Signal 3.1.10.3. I2C_CLK Signal 3.1.11. NFC Supplemental UIM Interface 3.1.11.1. UIM_POWER_SRC 3.1.11.2. UIM_POWER_SNK 3.1.11.3. UIM_SWP 3.1.11.4. NFC Supplemental UIM Interface Wiring Example 3.1.12. Communication-specific Signals 3.1.12.1. Suspend Clock 3.1.12.2. Status Indicators 3.1.12.3. W_DISABLE# Signal 3.1.12.4. Coexistence Signals 3.1.13. Reserved Pins 3.1.14. Vendor Defined 3.1.15. Optional Signals 3.1.15.1. VIO_CFG Signal 3.1.16. Socket 1 Connector Pinout Definitions 3.1.17. Socket 1 Based Soldered-down Module Pinouts 3.2. WWAN/SSD/Other Socket 2 Adapter Interface Signals 3.2.1. Power Sources and Grounds 3.2.2. PCI Express Interface 3.2.3. Power up Timing 3.2.4. M-PCIe 3.2.5. USB Interface 3.2.6. HSIC Interface 3.2.7. SSCI Interface 3.2.8. USB 3.1 Gen1 Interface 3.2.9. SATA Interface (Informative) 3.2.9.1. DEVSLP 3.2.9.2. DAS/DSS 3.2.10. User Identity Module (UIM) Interface 3.2.10.1. UIM_PWR 3.2.10.2. UIM_RESET 3.2.10.3. UIM_CLK 3.2.10.4. UIM_DATA 3.2.10.5. SIM_DETECT 3.2.11. Communication-specific Signals 3.2.11.1. Suspend Clock 3.2.11.2. Status Indicators 3.2.11.3. W_DISABLE# Signals 3.2.11.4. Coexistence Signals 3.2.12. Supplemental Communication-specific Signals 3.2.12.1. FULL_CARD_POWER_OFF# 3.2.12.2. RESET# 3.2.12.3. General Purpose Input Output Pins 3.2.12.3.1. GNSS Signals 3.2.12.3.2. Audio Signals 3.2.12.3.3. Second UIM Signals 3.2.12.3.4. RFU 3.2.12.3.5. IPC[0..7] Signals 3.2.12.3.6. WAKE_ON_WWAN# Signal 3.2.12.4. DPR Signal 3.2.12.5. Antenna Control 3.2.13. SSD Specific Signals 3.2.13.1. Reserved for MFG CLOCK and DATA 3.2.13.2. SMBus Interface 3.2.13.2.1. ALERT# Signal 3.2.13.2.2. SMB_DATA Signal 3.2.13.2.3. SMB_CLK Signal 3.2.14. Configuration Pins 3.2.15. Vendor Defined Pins 3.2.16. Optional Signals 3.2.16.1. VIO_CFG Signal 3.2.17. Power Loss Signals 3.2.17.1. PLN# Signal 3.2.17.2. PLA_S2# Signal 3.2.17.3. Timing Requirements for Power Loss Signals 3.2.18. Socket 2 Connector Pinout Definitions 3.2.18.1. Socket 2 Key B Pinout Definitions 3.2.18.2. Socket 2 Key C Pinout Definitions 3.3. SSD Socket 3 Adapter Interface Signals 3.3.1. Power Sources and Grounds 3.3.2. PCI Express Interface 3.3.3. SATA Interface (Informative) 3.3.3.1. DEVSLP 3.3.3.2. DAS/DSS 3.3.4. SSD Specific Signals 3.3.4.1. SUSCLK 3.3.4.2. PEDET 3.3.4.3. Reserved for MFG Clock and Data 3.3.4.4. Status Indicators (LED_1#) 3.3.4.5. SMBus Interface 3.3.5. Optional Signals 3.3.5.1. VIO_CFG Signal 3.3.5.2. PWRDIS 3.3.6. USB Interface 3.3.7. Power Loss Signals 3.3.7.1. PLN# Signal 3.3.7.2. PLA_S3# Signal 3.3.7.3. Timing Requirements for Power Loss Signals 3.3.8. Socket 3 Connector Pinout Definitions 3.4. BGA SSD Interface Signals 3.4.1. Power Sources and Grounds 3.4.2. PCI Express Interface 3.4.2.1. PCI Express Auxiliary Signals 3.4.3. SATA Interface (Informative) 3.4.4. SSD Specific Signals 3.4.4.1. SUSCLK 3.4.4.2. PEDET 3.4.4.3. Status Indicator (LED_1#) 3.4.4.4. RFU 3.4.4.5. DNU 3.4.4.6. HSB (Host-Specific Balls) 3.4.4.7. Non-Critical To Function (NCTF) 3.4.5. SSD Specific Optional Signals 3.4.5.1. CAL_P 3.4.5.2. RZQ_1 and RZQ_2 3.4.5.3. XTAL_OUT 3.4.5.4. XTAL_IN 3.4.5.5. JTAG Signals 3.4.5.6. SMBus Pins 3.4.5.6.1. ALERT# 3.4.5.6.2. SMB_DATA 3.4.5.6.3. SMB_CLK 3.4.5.7. DIAG0, DIAG1 3.4.5.8. Serial Peripheral Interface (SPI) Pins 3.4.5.9. PWR_ID[0:4] 3.4.6. Power Loss Signals 3.4.6.1. PLN# Signal 3.4.6.2. PLA_S3# Signal 3.4.7. BGA SSD Soldered-Down Module Pin-out 3.5. Electrical Budget 4. Electrical Requirements 4.1. 3.3 V Logic Signal Requirements 4.2. 1.8 V Logic Signal Requirements 4.3. Electrical Requirements for M.2 Adapters 4.3.1. Voltage Supply Power-on Sequencing 4.3.2. Voltage Supply Power-off Sequencing 4.4. Electrical Requirements for BGA SSDs 4.4.1. BGA SSD Voltage Supply Power-on Sequencing 4.4.2. BGA SSD Voltage Supply Power-off Sequencing 4.4.3. BGA SSD Power Ramp Timing 4.4.4. BGA SSD Power Rail Slew Rate 4.4.5. BGA SSD Power Rail Parameters 4.5. Compliance Eye Limits at the M.2 Connector 4.5.1. Add-in Card Transmitter Path Compliance Eye Diagrams at 8.0 GT/s 4.5.2. Add-in Card Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s 4.5.3. System Board Transmitter Path Compliance Eye Diagram at 8.0 GT/s 4.5.4. System Board Minimum Receiver Path Sensitivity Requirements at 8.0 GT/s 4.5.5. Add-in Card Transmitter Path Compliance Eye Diagrams at 16.0 GT/s 4.5.6. Add-in Card Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s 4.5.7. System Board Transmitter Path Compliance Eye Diagram at 16.0 GT/s 4.5.8. System Board Minimum Receiver Path Sensitivity Requirements at 16.0 GT/s 4.5.9. Add-in Card Transmitter Path Pulse Width Jitter (PWJ) limits at 16.0GT/s 4.5.10. Test Channels 4.5.11. Preset Test Requirements at 16.0 GT/s 4.6. Power 4.6.1. Direct VBAT Connection Option for WWAN Adapters 4.6.2. Adapter Power Rating 5. Platform Socket Pinout and Key Definitions 5.1. Connectivity Socket; Socket 1 5.1.1. DisplayPort Based Socket 1 (Mechanical Key A) On Platform 5.1.2. SDIO Based Socket 1 (Mechanical Key E) On Platform 5.1.3. Dual Key Add-in Card: Supports SDIO Based Socket 1 and DisplayPort Based Socket 1 5.2. WWAN+GNSS/SSD/Other Socket; Socket 2 5.2.1. Socket 2 Module Key B 5.2.1.1. Socket 2 Key B – Configuration Pin Definitions 5.2.1.2. Socket 2 Pinout (Mechanical Key B) On Platform 5.2.2. Socket 2 Key C 5.2.2.1. Socket 2 Pinout (Mechanical Key C) On Platform 5.3. SSD Socket; Socket 3 (Mechanical Key M) 5.4. Soldered Down Pinouts Definitions 6. Annex 6.1. Glossary 6.2. M.2 Signal Directions 6.3. Signal Integrity Requirements 8.0 GT/s 6.3.1. Test Fixture Recommendations 6.3.2. Suggested Top Mount Signal Integrity PCB Layout 6.3.3. Suggested Mid-mount Signal Integrity PCB Layout 6.4. Signal Integrity Requirements 16.0 GT/s 6.4.1. Standalone Connector Test Guidelines 6.4.2. Test Fixture Recommendations and Gold Finger Ground Voiding Guidelines to support 16.0 GT/s 6.4.3. Suggested Top Mount Signal Integrity PCB Layout 6.5. RF Connector Related Test Setups 6.5.1. VSWR Test Set-up Method for RF Connector Receptacles 6.5.2. Contact Resistance Measurement Setup and Test Procedure Example 6.6. Thermal Guideline Annex 6.6.1. Assumptions 6.6.1.1. Die Thermal Dissipation Overview 6.6.1.2. Component Overview 6.6.2. Generic System Environment Categories (Assumptions) 6.6.2.1. Adapter Slot Definitions by System 6.6.2.1.1. Systems with Fans 6.6.2.1.2. Systems without Fans 6.6.3. Assessing Thermal Design Power Capability 6.6.3.1. Use Cases 6.6.3.2. Extended Use Cases 6.6.3.3. Unpowered Adapter 6.6.3.4. Use Case Flexibility 6.6.4. Adapter Placement Advice 6.6.5. Skin Temperature Sensitivity to Adapter Power 6.6.6. General Applicability 6.6.7. Generic Assumptions for Adapter Arrangement 6.6.8. Examples 6.6.8.1. Notebook Category 6.6.8.1.1. Generic Motherboard Assumptions 6.6.8.1.2. System Layout Assumptions 6.6.8.1.3. Local Skin Temperature 6.6.8.1.4. Thermal Design Power Response – Notebook Category 6.6.8.2. Thin Platform Notebook with Fan Category 6.6.8.2.1. Generic Motherboard Assumptions 6.6.8.2.2. System Layout Assumptions 6.6.8.2.3. Adapter Placement Advice – Thin Platform Notebook 6.6.8.2.4. Local Skin Temperature 6.6.8.2.5. Thermal design Power Response – Thin Platform Notebook with Fan Category 6.6.8.3. Tablet without Fan Category 6.6.8.3.1. Generic Motherboard Assumptions 6.6.8.3.2. System Layout Assumptions 6.6.8.3.3. Local Skin Temperature 6.6.8.3.4. Thermal Design Power Response—Tablet Category 6.7. Examples of FULL_CARD_POWER_OFF# Sequences (Informative) 6.7.1. Example of Power On/Off Sequence 6.7.2. Example of Tablet Power On/Off Sequence 6.7.3. Shutdown Handshaking Process 6.7.4. Example of Very Thin Notebooks Power On/Off Sequence 6.8. Socket 2 Key C - Vendor Defined Pinout Examples 6.9. High Speed Differential Pair AC Coupling Capacitor Values and Capacitor Location Examples 6.9.1. AC Coupling Capacitor Values Per Respective Specification Definitions 6.9.2. AC Coupling Capacitor Location Examples 6.9.2.1. PCIe and USB3.1 AC Coupling Capacitor Location Examples 6.9.2.2. SATA-IO AC Coupling Capacitor Location Examples 6.9.3. AC Coupling Capacitor Scheme Compatibility Matrix 6.10. Eye Limits for SSIC at the M.2 Connector Appendix A. Acknowledgments