Optimizing PowerPC code : programming the PowerPC chip in assembly language

For computer programmers who have experience with high-level languages such as C or Pascal or with assembly language for another processor, introduces the concepts and relays some practical hints on writing efficient, robust code for Motorola's new PowerPC chip. Includes new concepts in RISC programming such as pipelining, compilers' tricks to produce fast code, corrections and additions to Motorola's documentation, and appendices with extended code forms and related mapping information. The CiP data does not include the subtitle. Annotation copyright Book News, Inc. Portland, Or. Chapter 1 Introduction 1 Purpose of Book 1 Intended Audience 1 Why Assembly Language on a RISC Processor? 2 PowerPC as a RISC ISA 5 Overview of this Book 7 Chapter 2 PowerPC Architecture Overview 9 Data Organization 9 Functional Units 12 Processor Registers 13 32- versus 64-bit Implementations 23 Chapter 3 Instruction Set Overview 27 Instruction Groups 27 Instruction Suffixes 28 Extended Instruction Forms 29 Obsolete Instructions 29 Optional Instructions 29 Notation 30 Chapter 4 Branch and Trap Instructions 35 Branch Instructions 35 Branch Prediction 47 Trap Instructions 50 System Linkage Instructions 54 Chapter 5 Load and Store Instructions 57 Loads and Stores 57 Load and Store Byte 59 Load and Store Halfword 60 Load and Store Word 61 Load and Store Doubleword 63 Load and Store Byte-Reversed Data 64 Load and Store Floating-Point Double-Precision Load and Store Floating-Point Single-Precision Load and Store Multiple 66 Load and Store String 68 Load and Store Synchronization 71 Obsolete Load String 72 Chapter 6 Integer Instructions 75 Addition 75 Subtraction 78 Multiplication 80 Division 81 Miscellaneous Arithmetic Instructions 83 Comparison Instructions 84 Logical (Boolean) Instructions 86 Obsolete Arithmetic Instructions 88 Chapter 7 Rotate and Shift Instructions 93 Rotation Masks 93 How Rotates and Shifts Update the CR 96 Rotate Instructions 97 Shift Instructions 102 Extended Rotate Instruction Forms 107 Multiple-Precision Shifts 115 Obsolete Rotate and Shift Instructions 129 Chapter 8 Floating-Point Instructions 135 Floating-Point Data Representation 135 Floating-Point Operation 142 Floating-Point Instructions 148 Floating-Point Conversions 155 Chapter 9 System Register Instructions 159 CR Instructions 159 FPSCR Instructions 162 MSR Instructions 163 SPR Instructions 164 User-Level SPR Extended Forms 164 Supervisor-Level SPR Extended Forms 166 Time Base Register Instructions 170 Segment Register Instructions 171 Chapter 10 Memory and Caches 173 Introduction 173 Memory and Cache Overview 174 Cache Architecture 176 PowerPC Cache Geometry 184 PowerPC Cache Coherency 185 PowerPC Storage Control Instructions 185 Virtual Memory 188 PowerPC Memory Management 192 PowerPC Memory Access Modes 196 PowerPC Lookaside Buffer Instructions 198 Chapter 11 Pipelining 201 What is a Pipeline? 201 Basic Pipeline Functions 202 PowerPC 601 Pipeline Description 205 Chapter 12 PowerPC 601 Instruction Timing 215 Reading the Timing Tables 215 Instruction Dispatch Timing 216 Fixed-Point Instruction Timings 219 Floating-Point Instruction Timings 225 Branch Instruction Timings 228 Cache Access Timings 238 Pipeline Synchronization 240 Abnormal Integer Conditions 243 Abnormal Floating-Point Conditions 245 Timing Pitfalls 248 Chapter 13 Programming Model 251 Register Usage Conventions 251 Table of Contents (TOC) 254 The Stack Pointer 255 Brief Interlude: Naming Conventions 261 Subroutine Calling Conventions 261 A Simple Subroutine Call 262 An Even Simpler Subroutine Call 268 Saving Registers on the Stack 270 Stack Frames 278 Passing Arguments to Routines 281 Retrieving Results from Routines 286 Stack Frames and alloca() 287 Linking with Global Routines 288 Chapter 14 Introduction to Optimizing 295 When to Optimize 295 Examining Compiled Code 297 Standard Optimizations 300 Chapter 15 Resource Scheduling 305 Types of Processor Resources 305 Pipeline Conflicts 306 Register Usage Dependencies 314 Memory Dependencies 334 Chapter 16 More Optimization Techniques 341 Keeping the Processor Busy 341 Increasing Scheduling Opportunities 344 Strength Reduction 346 Load / Store Ordering 350 Software Pipelining 351 Appendix A Instruction Set Summary 353 Appendix B Complete List of Mnemonics 643 Appendix C Register Bit Definitions 669 Appendix D Optimization Summary 677 Appendix E References & Further Reading 679 Index 681 Aims to help programmers optimize PowerPC code at the assembly-language level. The text covers key concepts to RISC programming, such as pipelining, and expands on and corrects limited Motorola documentation for the PowerPC chip.