Microprocessor-based parallel architecture : for reliable digital signal processing systems

"This book presents a distributed multiprocessor architecture that is faster, more versatile, and more reliable than traditional single-processor architectures. It also describes a simulation technique that provides a highly accurate means for building a prototype system in software. The system prototype is studied and analyzed using such DSP applications as digital filtering and fast Fourier transforms. The code is included as well, which allows others to build software prototypes for their own research systems. The design presented in Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems introduces the concept of a dual-mode architecture that allows users a dynamic choice between either a conventional or fault-tolerant system as application requirements dictate. This volume is a "must have" for all professionals in digital signal processing, parallel and distributed computer architecture, and fault-tolerant computing."--Provided by publisher Cover 1 Half Title 2 Title 4 Copyright 5 PREFACE 6 About the Authors 9 Table of Contents 10 Dedication 13 Chapter 1: INTRODUCTION 14 1.1: Statement of the Problem 14 1.1.1: Fault tolerance 15 1.1.2: Performance 15 1.2: Method of Attack 17 Chapter 2: FAULT-TOLERANT COMPUTING 20 2.1: Basic Definitions 20 2.2: Fault Tolerance Overview 21 2.3: Redundancy Techniques 23 2.3.1: Hardware redundancy 23 2.3.2: Software redundancy 24 2.3.3: Information redundancy 26 2.3.4: Time redundancy 26 2.4: Fault-Tolerant Communication Architectures 27 2.4.1: Reliable shared buses 28 2.4.2: Shared-memory interconnection networks 28 2.4.3: Loop architectures 30 2.4.4: Tree networks 31 2.4.5: Dynamically reconfigurable networks 32 2.4.6: Binary cube interconnection networks 33 2.4.7: Graph networks 34 2.5: Atomic Transactions 36 2.6: Communication Network Properties 37 2.7: Examples of Fault-Tolerant Systems 37 2.7.1: Tandem Non-Stop computer system 38 2.7.2: Stratus computer system 39 2.7.3: Electronic switching system 39 2.7.4: Space Shuttle computer system 40 2.7.5: Fault-tolerant multiprocessor 41 2.7.6: Software implemented fault tolerance 41 2.7.7: August Systems industrial control computers 43 2.7.8: The C.vmp system 43 2.8: Summary 44 Chapter 3: PARALLEL COMPUTING 46 3.1: Parallel Processing Overview and Definitions 46 3.2: Parallel Architecture Models 49 3.3: Operating System Overview 54 3.4: Real-Time Computing Overview 56 3.5: Summary 57 Chapter 4: DIGITAL SIGNAL PROCESSING AND PROCESSORS 60 4.1: Digital Signal Processing Overview 60 4.2: Basic Algorithms 61 4.2.1: Digital filters 61 4.2.2: Fast Fourier transforms 63 4.3: Digital Signal Processing Microprocessors 64 4.3.1: Specialized arithmetic hardware 65 4.3.2: Multiple buses 66 4.3.3: Pipelining 67 4.4: The DSP96002 Digital Signal Processor 68 4.4.1: Introduction 68 4.4.2: Programming model 70 4.4.3: Addressing modes 73 4.4.4: Instruction set 75 4.4.5: Host interfacing 81 4.5: Summary 84 Chapter 5: SYSTEM DESIGN 86 5.1: Premises and Goals 86 5.2: DSP Implementation Considerations 88 5.2.1: Digital filtering 88 5.2.2: Fast Fourier transformations 100 5.3: Redundancy Considerations 103 5.4: Communication Architecture Considerations 104 5.5: Static Redundancy Considerations 106 5.5.1: Hardware-based vs. software-based voting 108 5.5.2: Single-output fault-tolerant voting 110 5.5.3: Input selection 111 5.6: Fault-Tolerant Clock Synchronization 112 5.7: Communication Primitives 115 5.8: System Interface and Communication Design 116 5.8.1: Memory interface model 116 5.8.2: PE-to-PE interfacing 118 5.8.3: PE-to-output interfacing 119 5.8.4: Input-to-PE interfacing 120 5.9: Design Enhancements for a Dual-Mode Architecture 122 5.9.1 Dual-mode final-stage output interface design 123 5.9.2 Dual-mode initial-stage input interface design 125 5.10: Summary 127 Chapter 6: SYSTEM SIMULATION 130 6.1: Simulation Library Support 130 6.2: IEEE Single-Precision Conversion 131 6.3: System Simulation Overview 132 6.4: Simulation of PE-to-PE Communication 133 6.5: Simulation of PE-to-Output Communication 134 6.6: Simulation of Input-to-PE Communication 134 6.7: Summary 135 Chapter 7: PRELIMINARY TEST AND EVALUATION 136 7.1: Communication Primitives 136 7.2: Data Propagation 140 7.3: Digital Filtering 142 7.4: Fast Fourier Transformations 146 7.5: Fault Injection and Analysis 150 7.6: Analytical Analysis 152 7.7: Summary 158 Chapter 8: CONCLUSIONS 160 Appendix A: MULTIPROCESSOR SIMULATION LIBRARY FUNCTIONS 164 Appendix B: SIMULATION SOFTWARE LISTINGS 168 Appendix C: SYSTEM MACRO AND EQUATE SOFTWARE LISTINGS 180 Appendix D: PRELIMINARY TEST SOFTWARE LISTINGS 190 BIBLIOGRAPHY 270 INDEX 282 For all professionals in signal processing, parallel and distributed computer architecture, and fault-tolerant computing, this book presents a new distributed multiprocessor architecture which is faster and more versatile than traditional single-processor architectures.