Memory Architecture Exploration For Programmable Embedded Systems

Continuing advances in chip technology, such as the ability to place more transistors on the same die (together with increased operating speeds) have opened new opportunities in embedded applications, breaking new ground in the domains of communication, multimedia, networking and entertainment. New consumer products, together with increased time-to-market pressures have created the need for rapid exploration tools to evaluate candidate architectures for System-on-Chip (SoC) solutions. Such tools will facilitate the introduction of new products customized for the market and reduce the time-to-market for such products. While the cost of embedded systems was traditionally dominated by the circuit production costs, the burden has continuously shifted towards the design process, requiring a better design process, and faster turn-around time. In the context of programmable embedded systems, designers critically need the ability to explore rapidly the mapping of target applications to the complete system. Moreover, in today's embedded applications, memory represents a major bottleneck in terms of power, performance, and cost. In particular, Memory Architecture Exploration for Programmable Embedded Systems addresses efficient exploration of alternative memory architectures, assisted by a "compiler-in-the-loop" that allows effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system. The book concludes with a set of experiments demonstrating the utility of this exploration approach. The authors perform architecture and compiler exploration for a set of large, real-life benchmarks, uncovering promising memory configurations from different perspectives, such as cost, performance and power. Moreover, the authors compare the Design Space Exploration heuristic with a brute force full simulation of the design space, to verify that the heuristic successfully follows a true pareto-like curve. Such an early exploration methodology can be used directly by design architects to quickly evaluate different design alternatives, and make confident design decisions based on quantitative figures. Memory Architecture Exploration for Programmable Embedded Systems is designed for different groups in the embedded systems-on-chip arena. First, the book is designed for researchers and graduate students interested in memory architecture exploration in the context of compiler-in-the-loop exploration for programmable embedded systems-on-chip. Second, the book is intended for embedded system designers who are interested in an early exploration methodology, where they can rapidly evaluate different design alternatives, and customize the architecture using system-level IP blocks, such as processor cores and memories. Third, the book can be used by CAD developers who wish to migrate from a hardware synthesis target to embedded systems containing processor cores and significant software components. CAD tool developers will be able to review basic concepts in memory architectures with relation to automatic compiler/simulator software toolkit retargeting. Finally, since the book presents a methodology for exploring and optimizing the memory configuration for embedded systems, it is intended for managers and system designers who may be interested in the emerging embedded system design methodologies for memory-intensive applications. Cover......Page 1 Contents......Page 6 List of Figures......Page 10 List of Tables......Page 14 Preface......Page 16 Acknowledgments......Page 18 1.1 Motivation......Page 20 1.2 Memory Architecture Exploration for Embedded Systems......Page 21 1.3 Book Organization......Page 26 2.1 High-Level Synthesis......Page 28 2.2 Cache Optimizations......Page 29 2.3 Computer Architecture......Page 30 2.4 Disk File Systems......Page 31 2.5 Heterogeneous Memory Architectures......Page 32 2.5.1 Network Processors......Page 33 2.5.2 Other Memory Architecture Examples......Page 34 2.6 Summary......Page 35 3.1 Motivation......Page 36 3.2 Memory Estimation Problem......Page 37 3.3 Memory Size Estimation Algorithm......Page 39 3.3.1 Data-dependence analysis......Page 41 3.3.3 Determining the bounding rectangles......Page 42 3.3.4 Determining the memory size range......Page 43 3.4 Discussion on Parallelism vs. Memory Size......Page 44 3.5 Experiments......Page 46 3.6 Related Work......Page 47 3.7 Summary......Page 48 4.1 Motivation......Page 50 4.2.1 Our approach......Page 51 4.2.2 Illustrative example......Page 53 4.2.3 The Access Pattern based Memory Exploration (APEX) Approach......Page 56 4.2.4 Experiments......Page 58 4.2.5 Related Work......Page 64 4.3 Connectivity Architecture Exploration......Page 65 4.3.1 Our approach......Page 66 4.3.2 Illustrative example......Page 67 4.3.3 Connectivity Exploration Algorithm......Page 70 4.3.4 Experiments......Page 78 4.3.5 Related Work......Page 91 4.4 Discussion on Memory Architecture......Page 93 4.5 Summary and Status......Page 94 5.1 Motivation......Page 98 5.2 Memory Timing Extraction for Efficient Access Modes......Page 99 5.2.1 Motivating Example......Page 100 5.2.2 Our Approach......Page 102 5.2.3 TIMGEN: Timing extraction algorithm......Page 103 5.2.4 Experiments......Page 108 5.2.5 Related Work......Page 111 5.3 Memory Miss Traffic Management......Page 113 5.3.1 Illustrative example......Page 114 5.3.2 Miss Traffic Optimization Algorithm......Page 117 5.3.3 Experiments......Page 120 5.3.4 Related Work......Page 124 5.4 Summary......Page 126 6.1 Experimental setup......Page 128 6.2.1 The Compress Data Compression Application......Page 129 6.2.2 The Li Lisp Interpreter Application......Page 133 6.2.3 The Vocoder Voice Coding Application......Page 135 6.3 Summary of Experiments......Page 136 7.1 Summary of Contributions......Page 138 7.2 Future Directions......Page 139 References......Page 140 Index......Page 146