طراحی منطقی برای مدارهای مبتنی بر آرایه [منبع الکترونیکی] یک روش طراحی ساختاری

This book will show you how to approach the design covering everything from the circuit specification to the final design acceptance, including what support you can expect, sizing, timing analysis, power and packaging, various simulations, design verification, and design submission. cover......Page 1 Contents......Page 2 Preface......Page 5 Overview......Page 6 ASIC......Page 7 Demand And Supply......Page 9 eLearning - Next Best Thing......Page 10 The Array......Page 12 Design Tools - [2001]......Page 14 Framework Systems......Page 15 Full Custom Arrays......Page 16 Semi-Custom Arrays......Page 17 WHERE DO YOU START?......Page 19 Circuit Architecture......Page 20 Which Array Technology?......Page 21 Size......Page 23 Design-Support Issues......Page 26 Annotation......Page 27 Exercises......Page 32 Update 2000......Page 34 Design Sequence - Pre-Capture......Page 36 Circuit hardware specification......Page 37 Review of the available arrays......Page 38 Initial sizing of the circuit......Page 40 Selection of the array series......Page 41 Compute the path propagation delay......Page 43 Compute maximum internal current......Page 45 Review the design submission requirements......Page 46 Pre-Simulation Steps......Page 48 Perform design rules checking......Page 49 Perform testability analysis on the circuit.......Page 50 Simulation......Page 52 Functional simulation execution......Page 53 Vector Rules Checking......Page 54 At-speed simulation......Page 56 The Design Submission Through Prototype......Page 59 Submit the circuit - acceptance design......Page 60 Array Interfacing......Page 63 Review the Available Arrays......Page 66 Architectural Specification or Hardware Specification......Page 69 Array Sizing......Page 71 Array architecture......Page 76 Netlist......Page 79 Example: AMCC interface options......Page 80 Example - AMCC Arrays - Power Supply......Page 82 Interface cell functionality......Page 84 Hard and soft macros......Page 87 Refining Interface Requirements......Page 88 Dual-Function I/O Macros......Page 90 Thermal Diodes......Page 92 Final Interface Cell Utilization......Page 94 Example - BiCMOS Cell/PAD Utilization......Page 95 Drivers......Page 96 Exercises......Page 98 Case Study: Sizing A Design......Page 99 THE DESIGN......Page 100 SOLUTION - Q20000......Page 101 16:1 MUX......Page 104 Parity tree......Page 105 SIMULTANEOUSLY SWITCHING OUTPUTS......Page 106 FAN-OUT LOADS......Page 108 EVIEW OF SIZE - SECOND PASS......Page 112 THE SCHEMATICS......Page 116 Design Optimization......Page 121 Optimization Approaches......Page 123 DESIGN FOR SPEED......Page 124 Design to Improve Speed......Page 125 Alternative implementations......Page 127 Design To Reduce Internal Cell Utilization......Page 129 Design To Reduce I/O Utilization......Page 131 Design To Fit The Package......Page 132 Design To Reduce Power......Page 134 Design To Reduce Cost......Page 135 Basic Design For Circuit Testability......Page 137 Basic Design For Circuit Reliability......Page 138 Timing Analysis for Arrays......Page 139 Path Propagation Delay Overview......Page 140 Intrinsic Set-Up and Hold Time......Page 141 Maximum Operating Frequency;......Page 142 Interconnect Delays......Page 143 Annotation......Page 144 k-Factors......Page 147 Exercises......Page 150 Worst-Case Delay Multiplication Factors......Page 153 Front-Annotation......Page 155 Intermediate-Annotation......Page 156 Back-Annotation......Page 157 External Set-Up and Hold Times......Page 158 Case 1: When The Timing Specifications Are......Page 161 Case 2: When The Timing Specifications Are Worst-Case......Page 162 Example - AMCC Q20000 Bipolar Series......Page 165 Case Study: Preventing Hold Violations Due To Clock Skew......Page 168 Overcoming Hold Time Error......Page 169 Design Check......Page 170 Computing Hold Time in the Register Example......Page 171 DC Power in a Bipolar Array......Page 173 DC Power in a BiCMOS Array......Page 174 AC Power......Page 176 Worst-case Power......Page 177 Power Reduction Techniques......Page 180 The Macros and Their Options......Page 181 Power-Down and Conditional Geometry - Bipolar......Page 182 Design Rules for Power Reduction AMCC......Page 183 Steps To Compute Maximum Worst-Case......Page 185 AC Macro Power Dissipation......Page 186 Steps Required To Compute DC Power......Page 187 Exercises......Page 191 Case Study: AC Power Computation......Page 192 Total Power Dissipation......Page 195 Simulation......Page 196 Simulators - The Tools......Page 198 AMCC's RaceCheck......Page 199 Fault-Grading......Page 201 Testability Analysis......Page 202 Simulation Rules......Page 203 At-Speed Simulation For Timing Verification......Page 204 AC Tests......Page 205 Hazards......Page 207 Case Study: Simulation......Page 210 MUX Enable......Page 212 The Simulations......Page 213 Parametric Simulation......Page 214 At-Speed Simulation......Page 217 AC Test......Page 223 Faults and Fault Detection......Page 226 Fault Types......Page 227 Single Stuck-At Faults......Page 228 The Problem......Page 230 Formation Rules for the Existence Function......Page 231 Selecting a Chain......Page 233 Simple Gates - Sequences......Page 234 Extension to Three-state and Bidirectional Structures......Page 236 Case Study - 16:1 MUX D Flip/Flop......Page 237 2:1 MUX Example......Page 239 3:1 MUX Example......Page 240 16:1 MUX Actual Test Vectors......Page 241 Case Study: AMCC Design......Page 242 Functional Simulation Submission (Required)......Page 247 At-Speed Simulation Submission......Page 248 AC Tests Path Delay Vector......Page 249 Parametric Vectors (Required Or......Page 250 AMCC Simulation Forms - Vocabulary......Page 251 Glossary......Page 253 Symbols......Page 270 This text presents training material on arrays for practicing engineers. It uses examples, checklists and basic structural design to train engineers in array-integrated circuits, and is a supplement to materials provided by manufacturers.