Logic and architecture synthesis : state-of-the-art and novel approaches : IFIP Workshop on Logic and Architecture Synthesis, 1994

This book describes several methods and systems solving one of the highlighted problems within computer aided design, namely architectural and logic synthesis. The book emphasises the most recent technologies in high level synthesis, concentrating on applicative studies and practical constraints or criteria during synthesis. Logic and Architecture Synthesis concentrates on the practical problems involving automatic synthesis of designs. It is essential reading for researchers and CAD Managers working in this area. Front Matter....Pages N1-xii Front Matter....Pages 1-1 Boolean Optimization Using Implicit Techniques....Pages 3-14 Multiple-Level Logic Optimization with Boolean Relations....Pages 15-25 BONSAI: A pragmatic approach to Logic Synthesis and Formal Verification....Pages 26-37 Front Matter....Pages 39-39 Combined approach of ROBDDs and structural analysis in the mapping and matching of logic functions....Pages 41-56 Efficient ROBDD based computation of common decomposition functions of multi-output boolean functions....Pages 57-63 Circuit depth optimization by BDD based function decomposition....Pages 64-69 Symmetry Based Variable Ordering for ROBDDs....Pages 70-81 Front Matter....Pages 83-83 Circuit clustering and partitioning for system implementations....Pages 85-96 Circuit Partitioning For FPGAs....Pages 97-106 Front Matter....Pages 107-107 Balanced multilevel decomposition and its applications in FPGA-based synthesis....Pages 109-115 Disjoint Decomposition for LUT FPGA Synthesis....Pages 116-123 Performance Comparison of Logic Block Units Implemented in FPGA’s Families....Pages 124-135 Front Matter....Pages 137-137 Area Optimization of Bit-Parallel Custom Data Paths....Pages 139-150 DataPath regularity extraction....Pages 151-157 EPR — a Synthesis Tool for Speed Optimization....Pages 158-165 Front Matter....Pages 167-167 ROM-based Multi Thread Controller....Pages 169-175 State Assignment Selection for FPGAs and CPLDs....Pages 176-182 Control optimization and hardware translation of Esterel programs....Pages 183-189 SEC state assignment selection: consequences on the area and reliability of fault-tolerant controllers....Pages 190-196 On Multi-Cycle False Paths in Sequential Circuits....Pages 197-208 Front Matter....Pages 209-209 Low Power VLSI Design Method for Data Path and Controllers....Pages 211-222 Behavioral synthesis: control schemes in question....Pages 223-229 Front Matter....Pages 231-231 RAM-based architectural synthesis....Pages 233-244 Module generators and their integration in an architectural systhesis system....Pages 245-251 Towards Better Accounting of Physical Design Effects in High-Level Synthesis....Pages 252-258 Front Matter....Pages 259-259 Delay/Area Trade-Off Exploration Using an Architectural Jiggling Algorithm....Pages 261-267 The Influence on Synthesis of Modern Computer Arithmetic....Pages 268-279 Adders synthesis....Pages 280-286 Front Matter....Pages 287-287 High-Level Synthesis: A Critical Assessment....Pages 289-299 High Level Synthesis by Systematic Derivation of Vision Automata from Emulation Results....Pages 300-306 Synthesis: From Digital Signal Processing Specifications to Layout....Pages 307-313 BDD application to mutual exclusion testing in high-level synthesis....Pages 314-320 Front Matter....Pages 321-321 VHDL-based behavioral synthesis: can it pay off for telecom ASICs ?....Pages 323-329 An Asynchronous Microprocessor in Gallium Arsenide....Pages 330-336 Front Matter....Pages 337-337 Optimizing the Communication Overheads during the Allocation of Global Memories and Busses....Pages 339-345 Optimal and Robust Scheduling of Communications in Bus Architectures....Pages 346-352 Front Matter....Pages 353-353 Cosynthesis In CASTLE....Pages 355-366 Optimization of Heterogeneous Multiprocessors for Complex Image Processing Applications....Pages 367-373 Self-test with deterministic test pattern generators....Pages 377-388 Back Matter....Pages 389-390