LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers (The Springer International Series in Engineering and Computer Science Book 843)

LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers fits in the quest for complete CMOS integration of wireless receiver front-ends. With a combined discussion of both RF and ESD performance, it tackles one of the final obstacles on the road to CMOS integration. The book is conceived as a design guide for those actively involved in the design of CMOS wireless receivers. The book starts with a comprehensive introduction to the performance requirements of low-noise amplifiers in wireless receivers. Several popular topologies are explained and compared with respect to future technology and frequency scaling. The ESD requirements are introduced and related to the state-of-the-art protection devices and circuits. LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers provides an extensive theoretical treatment of the performance of CMOS low-noise amplifiers in the presence of ESD-protection circuitry. The influence of the ESD-protection parasitics on noise figure, gain, linearity, and matching are investigated. Several RF-ESD co-design solutions are discussed allowing both high RF-performance and good ESD-immunity for frequencies up to and beyond 5 GHz. Special attention is also paid to the layout of both active and passive components. LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers offers the reader intuitive insight in the LNA?s behavior, as well as the necessary mathematical background to optimize its performance. All material is experimentally verified with several CMOS implementations, among which a fully integrated GPS receiver front-end. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject. Contents......Page 6 Abstract......Page 10 List of Symbols and Abbreviations......Page 11 1.1 The Growth of the Wireless Communication Market......Page 16 1.2 Evolution to CMOS RF......Page 18 1.3 CMOS, RF and ESD......Page 20 1.4 Outline of this Book......Page 21 2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation......Page 23 2.2.2 SNR and Noise Figure......Page 25 2.2.3 Impedance Matching, Power Matching, Noise Matching......Page 26 2.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain......Page 27 2.2.5 Intermodulation Distortion......Page 29 2.3.1 MOS Model for Hand Calculations......Page 31 2.3.2 Linearity of the short-channel MOS transistor......Page 32 2.3.3 Non-Quasi Static Model......Page 33 2.3.4 Extended MOS Model for Simulation......Page 35 2.4.2 Thermal Noise in MOS transistors......Page 36 2.4.2.2 Induced Gate Noise......Page 37 2.4.4 Shot Noise......Page 38 2.5.1 Cascading Non-Ideal Building Blocks......Page 39 2.5.2 Wireless Receiver Architectures......Page 41 2.5.3 LNA Requirements......Page 42 2.6.1 The Inductively Degenerated Common Source LNA......Page 47 2.6.2 The Common-Gate LNA......Page 57 2.6.3 Shunt-Feedback Amplifier......Page 62 2.6.4 Image Reject LNA’s......Page 64 2.6.5 Highly Linear Feedforward LNA......Page 65 2.6.7 Current Reuse LNA with Interstage Resonance......Page 66 2.6.8 Transformer Feedback LNA......Page 67 2.7 Conclusion......Page 68 3.1 Introduction......Page 69 3.2.1 Human Body Model......Page 70 3.2.2 Machine Model......Page 71 3.2.3 Charged Device Model......Page 72 3.2.4 Transmission Line Pulsing......Page 73 3.3.1 ESD-Protection Devices......Page 76 3.3.2 ESD-Protection Topologies......Page 82 3.4 Conclusion......Page 86 4.2 The Non-Quasi Static Gate Resistance......Page 87 4.2.1 Influence of r[sub(g)],NQS on Z[sub(in)], G[sub(T)] and IIP3......Page 88 4.2.2 Influence of r[sub(g)],NQS on the Noise Figure......Page 89 4.3 Parasitic Input Capacitance......Page 92 4.3.1 Impact of C[sub(p)]......Page 93 4.3.2 Impact of C[sub(p)] Non-Linearity......Page 99 4.3.3 Impact of the Finite Q of C[sub(p)]......Page 102 4.4 Miller Capacitance......Page 103 4.5 Optimization of the Cascode Transistor......Page 105 4.6 Output Capacitance Non-Linearity......Page 106 4.7 Impact of a Non-Zero S[sub(11)]......Page 109 4.8.1 Load Impedance Constraints......Page 110 4.8.2 Output Matching......Page 112 4.9 LNA Bandwidth......Page 114 4.10.1 RF Bonding Pads......Page 115 4.10.2 On-Chip Inductors......Page 116 4.10.3 The Amplifying Transistor......Page 118 4.11 The Common-Gate LNA Revisited......Page 119 4.12 Conclusion......Page 123 5.1 Introduction......Page 125 5.2.1 Introduction......Page 126 5.2.2 General Performance......Page 127 5.2.3 Design and Layout of the ESD Protection Diodes......Page 129 5.2.4 Non-Linearity of Input ESD Protection Diodes......Page 130 5.3 ESD-Protection within a II-Type Matching Network......Page 133 5.4 Inductive ESD-Protection......Page 137 5.5 Comparison......Page 140 5.6.1 Distributed ESD-Protection......Page 142 5.8 Conclusion......Page 144 6.2.1 The GPS Power Levels......Page 146 6.2.2 Topology......Page 147 6.2.3 Design......Page 148 6.2.4 Layout......Page 152 6.2.5 Experimental Results......Page 154 6.2.6 Discussion and Comparison......Page 157 6.3.1 The Complete GPS Receiver Front-End......Page 160 6.3.2 The Low Noise Amplifier......Page 163 6.3.3 Results......Page 166 6.3.4 Conclusion......Page 171 6.4.1 5 GHz Wireless LAN......Page 172 6.4.2 Design......Page 173 6.4.3 Results......Page 178 6.5 Conclusion......Page 182 7 Conclusions......Page 183 A Fundamentals of Two-Port Noise Theory......Page 185 D......Page 187 L......Page 188 S......Page 189 W......Page 190 By Paul Leroux And Michiel Steyaert. Includes Bibliographical References (p. [179]-187) And Index.