تکنیک‌های چیدمان برای طراحان مدار مجتمع

This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today's manufacturing techniques and how they impact design rules. You will understand how to build common high frequency devices such as inductors, capacitors and T-coils, and will also learn strategies for dealing with high-speed routing both on package level and on-chip applications. Numerous algorithms implemented in Python are provided to guide you through how extraction, netlist comparison and design rule checkers can be built. The book also helps you unravel complexities that effect circuit design, including signal integrity, matching, IR drop, parasitic impedance and more, saving you time in addressing these effects directly. You will also find detailed descriptions of software tools used to analyze a layout database, showing you how devices can be recognized and connectivity accurately assessed. The book removes much of fog that often hides the inner workings of layout related software tools and helps you better understand: the physics of advanced nodes, high speed techniques used in modern integrated technologies, and the inner working of software used to analyze layout databases. This is an excellent resource for circuit designers implementing a schematic in a layout database, especially those involved in deep submicron designs, as well as layout designers wishing to deepen their understanding of modern layout rules. Artech House Integrated Microsystems Library Layout Techniques for Integrated Circuit Designers 2 Contents 6 Preface 12 Chapter 1 Introduction 14 Part I: Manufacturing and Physical Layout Techniques 16 Chapter 2 Preliminaries 18 2.1 Silicon Manufacturing Basics 18 2.1.1 Basic Overview 19 2.1.2 Epitaxy 21 2.1.3 Oxidation 23 2.1.4 Photolithography 24 2.1.5 Etching 36 2.1.6 Doping 38 2.1.7 Deposition 40 2.1.8 Planarization 45 2.1.9 Wafer Stack-Up 46 2.1.10 Thinning 46 2.1.11 Singulation (Dicing/Cutting) 47 2.1.12 Bonding 48 2.1.13 Bumping 48 2.1.14 Packaging 48 2.1.15 Wafer-Level Probe Test 48 2.1.16 Final Test 49 2.2 Semiconductor Yield 49 2.2.1 Functional Yield 50 2.2.2 Parametric Yield 53 2.3 Layout Database Formats 53 2.3.1 Calma and GDSII 53 2.3.2 OASIS and Open Access 54 2.4 Schematic Netlist Formats 55 2.4.1 SPICE Format 55 2.4.2 CDL Format 60 2.4.3 Spectre Format 60 2.5 Simulation Output Formats 60 2.6 Formats Used in the Book 62 2.7 Summary 62 Exercises 62 References 63 Chapter 3 Device Formation in Layout 66 3.1 Process Stack-Up 66 3.2 Fundamental Devices 67 3.2.1 Silicide Formation 67 3.2.2 Resistors 68 3.2.3 Maxwell’s Equations 77 3.2.4 Capacitors 78 3.2.5 Inductors 81 3.2.6 Transmission Lines 84 3.2.7 MOSFET Devices 85 3.2.8 Bipolar Transistor Devices 97 3.2.9 Summary of Device Manufacturing 101 3.3 Device Matching 101 3.3.1 Process-Related Causes of Mismatch 101 3.3.2 Layout Strategies to Minimize Mismatch 103 3.3.3 Design Strategies to Reduce the Effect of Mismatch 106 3.4 Manufacturing Challenges: Design Rules 107 3.4.1 Design Rule Derivations 108 3.4.2 Width Rules 109 3.4.3 Spacing Rules 114 3.4.4 Enclosure/Overlap Rules 120 3.4.5 Area Rules 123 3.4.6 Antenna Rules 123 3.4.7 Density Rules 123 3.5 Future Directions 125 3.6 Summary 126 Exercises 126 References 126 Chapter 4 Layout with Ultrasmall Geometry CMOS Technologies 128 4.1 Small Geometry Effects 128 4.1.1 Thin Metal Effects 129 4.1.2 Strain Effects 140 4.1.3 Well Proximity Effect 149 4.1.4 Substrate Contact Distance Requirements 152 4.1.5 EM and IR Drop 153 4.2 Small Geometry CMOS Flow 158 4.2.1 Strategies to Manage High-Resistance Interconnect 159 4.2.2 Strategies to Manage Parasitic Capacitance 162 4.2.3 Strategies to Manage Parasitic Inductance 163 4.2.4 Overall Parasitic Strategies 167 4.3 Summary 168 Exercises 168 References 168 Chapter 5 Layout with Bipolar Technologies SiGe 170 5.1 Introduction 170 5.2 Process Flow 172 5.2.1 Physics of SiGe Bipolar Transistors 172 5.2.2 Collector Formation 174 5.2.3 Base Formation 175 5.2.4 Emitter Formation 176 5.2.5 Parasitics of Bipolar Transistors 179 5.2.6 PNP Transistors 181 5.2.7 Future Direction of SiGe transistors 181 5.3 Layout Flow 182 5.3.1 SIGe Technology Metallization 182 5.3.2 Transistor Layout Topologies 182 5.4 Other Technologies 184 5.4.1 InP HBT 185 5.4.2 GaAs HBT 185 5.4.3 Comparison of Different HBT Technologies 185 5.5 Summary 186 References 186 Chapter 6 Aspects of High-Speed Layout 10–100+ GHz 188 6.1 Single-Ended Transmission Lines On-Chip 188 6.1.1 Layout Applications 192 6.2 Interface to Package and Circuit Board 195 6.2.1 Impedance-Matching Review 195 6.2.2 S-Paramters: What Does Matching Mean? 197 6.2.3 Impedance Matching: Circuit-Level Analysis 199 6.2.4 T-Coil Theory 203 6.2.5 Summary 211 6.3 Coupled Transmission Lines On-Chip 211 6.3.1 Fundamental Properties 211 6.3.2 Power Waves 213 6.3.3 Eigenmodes 214 6.3.4 Solution with Eigenmodes 214 6.3.5 Examples of Coupled Transmission Lines 215 6.4 Inductors and Capacitors at High Frequencies 218 6.4.1 Skin Effect 218 6.5 Layout Strategies 220 6.5.1 High-Speed Analog Blocks 220 6.5.2 Analog and Digital Block Coexistence 224 6.6 Summary 225 Exercises 226 References 227 Part II: Layout Verification Techniques 228 Chapter 7 Extraction Techniques 230 7.1 Introduction 230 7.2 Basic Geometric Algorithms on Polygons 230 7.2.1 Definition of Polygons for Use in Layout Databases 231 7.2.2 Geometric Operations on Polygons 234 7.2.3 Geometric Operations in the Literature 252 7.3 Device Recognition Algorithms 253 7.3.1 Basic Technology 253 7.3.2 Supporting Software Architecture 254 7.3.3 Device Recognition Fundamentals 255 7.4 An Efficient Search Algorithm: k-d Tree 273 7.5 Connectivity Algorithms 274 7.5.1 Flat Layout Extraction 275 7.5.2 Hierarchical Layout Extraction 277 7.6 Parasitic Device Extraction 279 7.7 Summary 280 Exercises 280 References 281 Chapter 8 Netlist Comparators 284 8.1 Historical Development 284 8.2 Mathematical Basis 285 8.2.1 Graph Theory Definitions 285 8.2.2 Graph Isomorphism Problem 285 8.3 A Few Simple Examples on Comparing Netlists 287 8.3.1 Some Specific Situations 287 8.4 A Python Implementation 296 8.4.1 Node Connectivity Algorithm 298 8.4.2 Build a Match Matrix 299 8.4.3 Single Matching Algorithm 300 8.4.4 Matrix AND Operation 301 8.4.5 Isomorphism Verification Algorithm 301 8.4.6 Symmetry Match 302 8.4.7 Various Administrative Routines 303 8.4.8 Netlist Comparator 303 8.4.9 Various Improvements 305 8.5 A Larger Example with Unmatched Netlists 307 8.5.1 LVS Debug Report 307 8.5.2 A Mismatched Pair of Netlists 308 8.5.3 Summary 313 8.6 Other Algorithms 314 8.7 A Real-World LVS Flow for Integrated Circuits 314 8.8 Summary 315 Exercises 315 References 315 Chapter 9 Design Rule Checkers 316 9.1 Implementations of Design Rules 317 9.1.1 Basic Data Structure 317 9.1.2 Implementing Basic Width Rules 318 9.1.3 Implementing Basic Spacing Rules 322 9.1.4 Interdependent Spacing and Width Rules 325 9.1.5 Overlap and Enclosure Rules 329 9.1.6 Notch Rules 333 9.1.7 Antenna Rules 335 9.1.8 Area Rules 337 9.1.9 Density Rules 338 9.1.10 Colorization and Related Complexities 340 9.2 Summary 340 Exercies 340 References 340 Acronyms and Abbreviations 342 Index 348 Integrated,circuits;,Micorsystems;,CMOS;,Artech,House;,978-1-63081-910-1 Integrated circuits,Micorsystems,CMOS,Artech House,978-1-63081-910-1