JEDEC STANDARD. GRAPHICS DOUBLE DATA RATE (GDDR6) SGRAM STANDARD. JESD250D (Revision of JESD250C, February 2021)

Title Page Table of Contents List of Figures List of Tables 1 Scope 2 GDDR6 SGRAM Standard Overview 2.1 Features 2.2 Functional Description 2.3 Definition of Signal State Terminology 2.4 Definition of Clocking Terminology 2.5 Clocking Table 1 — Example Clock and Interface Signal Frequency Relationship Figure 1 — GDDR6 Clocking and Interface Relationship Figure 2 — Block Diagram of an Example Clock System 2.6 State Diagram Figure 3 — Simplified State Diagram 3 Initialization 3.1 Power-up Sequence Figure 4 — Power-up Initialization Table 2 — Device Initialization Timings Table 3 — CA Termination Table 4 — CK Termination 3.2 Initialization with Stable Power Figure 5 — Initialization with Stable Power 3.3 Vendor ID Table 5 — Vendor ID to DQ Mapping - ID1 (MR3 OP[7:6] = 01) Table 6 — Vendor ID to DQ Mapping - ID2 (MR3 OP[7:6] = 11) Table 7 — Manufacturers Vendor Code Table 8 — Internal WCK Table 9 — Channel Density Table 10 — WCK Granularity Table 11 — WCK Frequency Table 12 — VDDQ Off Table 13 — Programmable P2BR Table 14 — PRBS Table 15 — RFM Table 16 — RAA Initial Management Threshold (RAAIMT) Table 17 — RAA Maximum Management Threshold (RAAMMT) Table 18 — RAA Counter Decrement per REF Command Figure 6 — Vendor ID Timing Diagram 4 Address 4.1 Command And Addressing Table 19 — Addressing Scheme 4.2 Command Address Bus Inversion (CABI) Figure 7 — Example of Command Address Bus Inversion Logic Figure 8 — Command Address Bus Inversion (CABI) Flow Diagram 4.3 Bank Groups Table 20 — Bank Groups Table 21 — Command Sequences Affected by Bank Groups Figure 9 — tCCDS and tCCDL 5 Training 5.1 Interface Training Sequence Figure 10 — Interface Training Sequence 5.2 Command Address Training Figure 11 — Command Address Training Timing - Single Pass Table 22 — AC Timings in Command Address Training Mode Figure 12 — Multi pass CA Training Timings Figure 13 — Example of CADT Self Refresh - Multi Pass Figure 14 — Example of CA Training - Multi Pass Table 23 — CA to Data Mapping in CA Training Mode 5.3 WCK2CK Training Figure 15 — Example WCK2CK Training Sequence Figure 16 — Example WCK2CK Training Sequence with WCK Stopping Figure 17 — EDC Pin Behavior for WCK2CK Training with Internal WCK Figure 18 — Internal WCK Divider Circuit Table 24 — Phase Detector and EDC behavior Figure 19 — Normal Mode Figure 20 — Pin Mode (Optional) Table 25 — An Example of WCK2CK Training Simplified for Normal Mode and PIN Mode Figure 21 — WCK2CK Timings for WCK QDR Ratio Figure 22 — WCK2CK Timings for WCK DDR Ratio 5.4 READ Training Table 26 — LDFF and RDTR Timings Figure 23 — Data Paths used for Read and Write Training Figure 24 — LDFF Command Figure 25 — LDFF Command Address to DQ/DBI_n/EDC Mapping Figure 26 — RDTR Command 5.5 WRITE Training Table 27 — WRTR and RDTR Timings Figure 27 — WRTR Command Figure 28 — Write Training using WRTR and RDTR Commands 6 Mode Registers Figure 29 — Mode Registers Overview 6.1 Mode Register 0 (MR0) Figure 30 — Mode Register 0 (MR0) Definition 6.2 Mode Register 1 (MR1) Figure 31 — Mode Register 1 (MR1) Definition 6.3 Mode Register 2 (MR2) Figure 32 — Mode Register 2 (MR2) Definition Figure 33 — Impedance Offsets 6.4 Mode Register 3 (MR3) Figure 34 — Mode Register 3 (MR3) Definition 6.5 Mode Register 4 (MR4) Figure 35 — Mode Register 4 (MR4) Definition 6.6 Mode Register 5 (MR5) Figure 36 — Mode Register 5 (MR5) Definition 6.7 Mode Register 6 (MR6) and Mode Register 9 (MR9) Figure 37 — Mode Register 6 (MR6) Definition Figure 38 — Mode Register 9 (MR9) Definition Figure 39 — VREFD Options Table 28 — VREFD Level Figure 40 — VREFD Circuit and Range Figure 41 — VREFD and DFE Settling Time 6.8 Mode Register 7 (MR7) Figure 42 — Mode Register 7 (MR7) Definition 6.9 Mode Register 8 (MR8) Figure 43 — Mode Register 8 (MR8) Definition 6.10 Mode Register 10 (MR10) Figure 44 — Mode Register 10 (MR10) Definition Figure 45 — VREFC Options 6.11 Mode Register 11 (MR11) Figure 46 — Mode Register 11 (MR11) Definition Table 29 — Example of PASR 2-Bank and Row Segment Masking in Self Refresh Mode 6.12 Mode Register 12 (MR12) Figure 47 — Mode Register 12 (MR12) Definition 6.13 Mode Register 13 (MR13) Figure 48 — Mode Register 13 (MR13) Definition 6.14 Mode Register 14 (MR14) Figure 49 — Mode Register 14 (MR14) Definition 6.15 Mode Register 15 (MR15) Figure 50 — Mode Register 15 (MR15) Definition Figure 51 — Mode Register Enable 7 Operation 7.1 Commands Table 30 — Truth Table - Commands 7.2 Command, Address, and WRITE Data Input Timings Figure 52 — CA and CKE_n Input Timings Figure 53 — Data Input Timings 7.3 No Operation (NOP) 7.4 Mode Register Set Figure 54 — MRS Command Figure 55 — Mode Register Set Timings 7.5 Row Activation Figure 56 — ACTIVATE Command Figure 57 — Bank Activation Command Cycle 7.6 Bank Restrictions Figure 58 — tRRD and tFAW 7.7 WRITE (WOM) Figure 59 — WRITE Command Figure 60 — WRITE Lane Timings Figure 61 — Single WRITE without EDC (WCK DDR Mode) Figure 62 — Single WRITE without EDC (WCK QDR Mode) Figure 63 — Single WRITE with EDC (Full Data Rate) Figure 64 — Single WRITE with EDC (Half Data Rate) Figure 65 — Non-Gapless WRITEs Figure 66 — Gapless WRITEs Figure 67 — WRITE to READ Figure 68 — WRITE to PRECHARGE 7.8 WRITE Data Mask (DM) Table 31 — DM State Figure 69 — WRITE-With-Doublebyte-Mask Command Table 32 — WDM Mapping x16 Mode Table 33 — Example WDM x16 Mode Table 34 — WDM Mapping x8 Mode Table 35 — Example WDM x8 mode Figure 70 — WDM Timing Figure 71 — WRITE-With-Singlebyte-Mask Command Table 36 — WSM Mapping x16 Mode Table 37 — Example WSM x16 Mode Table 38 — WSM Mapping for x8 Mode Table 39 — WSM Mapping for x8 Mode Table 40 — Example WSM Figure 72 — WSM Timing 7.9 Masked Write Data Timing Constraints Figure 73 — WDM and WSM Timing with tCCDMW 7.10 READ Figure 74 — READ Command Figure 75 — READ Lane Timing Figure 76 — Single READ without EDC (WCK DDR Mode) Figure 77 — Single READ without EDC (WCK QDR Mode) Figure 78 — Single READ with EDC (Full Data Rate) Figure 79 — Single READ with EDC (Half Data Rate) Figure 80 — Non-Gapless READs Figure 81 — Gapless READs Figure 82 — READ to WRITE Figure 83 — READ to PRECHARGE 7.11 DQ Preamble Figure 84 — DQ Preamble Pattern Figure 85 — Preamble Timing Diagram 7.12 RDQS Mode Figure 86 — RDQS Mode Timings 7.13 READ and WRITE Data Bus Inversion (DBI) Figure 87 — Example of Data Bus Inversion Logic for READs Figure 88 — Example of Data Bus Inversion Logic for WRITEs Figure 89 — DBI Flow Diagram 7.14 Error Detection Code (EDC) Table 41 — Error Correction Details Figure 90 — EDC Calculation Matrix Table 42 — EDC Timing Table 43 — EDC Pin Behavior 7.15 PRECHARGE Figure 91 — PRECHARGE Command 7.16 Auto PRECHARGE 7.17 REFRESH and PER-BANK / PER-2-BANK REFRESH Figure 92 — REFRESH Command Figure 93 — REFab Timings Figure 94 — Postponing REFab Commands (Example) Figure 95 — REFpb / REFp2b Timings Figure 96 — Sets of REFpb Commands Table 44 — Refresh Counter Increments - REFpb Figure 97 — Sets of REFp2b Commands Table 45 — Refresh Counter Increments - REFp2b (LSB) Table 46 — Refresh Counter Increments - REFp2b (MSB) Table 47 — REFab and REFp2b Command Scheduling Requirements 7.18 REFRESH Management 7.19 SELF REFRESH Figure 98 — SELF REFRESH Entry Command Table 48 — Pin States During Self Refresh Figure 99 — Self Refresh Entry and Exit 7.20 Hibernate SELF REFRESH Figure 100 — Hibernate Self Refresh 7.21 Hibernate SELF REFRESH with VDDQ Off Figure 101 — Hibernate Self Refresh with VDDQ Off Entry and Exit 7.22 Power-down Figure 102 — Power-Down Entry and Exit Table 49 — Pin States During Power-Down 7.23 Command Truth Tables Table 50 — Truth Table – CKE_n Table 51 — Truth Table – Current State Bank n – Command To Bank n Table 52 — Truth Table – Current State Bank n – Command To Bank m Table 53 — Auto Precharge Enabled/Disabled and PREab / PREpb Timings 7.24 Clock Frequency Change Sequence 7.25 Dynamic Voltage Switching (DVS) Figure 103 — DVS Sequence 7.26 Temperature Sensor Table 54 — Temperature Sensor Readout Pattern Figure 104 — Temperature Sensor Readout Characteristics 7.27 Duty Cycle Corrector (DCC) Table 55 — DCC Timings Figure 105 — Example WCK2CK Training Sequence with DCC Table 56 — DCC Control Signals 8 Operating Conditions 8.1 Absolute Maximum Ratings Table 57 — Absolute Maximum Ratings 8.2 Pad Capacitances Table 58 — Silicon Pad Capacitance 8.3 Package Electrical Specification Table 59 — GDDR6 SGRAM Package Electrical Specifications 8.4 Package Thermal Characteristics Table 60 — Thermal Characteristics 8.5 Electrostatic Discharge Sensitivity Characteristics Table 61 — Electrostatic Discharge Sensitivity Characteristics 8.6 AC and DC Operating Conditions Table 62 — DC Operating Conditions Table 63 — AC Operating Conditions (For Design only11) Figure 106 — Voltage Waveform Figure 107 — Clock Waveform Figure 108 — Definition of Differential AC-swing and “Time above AC-level” tDVAC 8.7 POD I/O System Figure 109 — System Configurations Figure 110 — Initiator I/O Cell Figure 111 — Target I/O Cell Table 64 — POD I/O Sub Cells, 120 Ohm Based Figure 112 — PMOS Calibration Figure 113 — NMOS Calibration 8.8 IDD and IPP Parameters and Test Conditions Figure 114 — Measurement Setup for IDD and IPP Measurements Table 65 — IDD Specifications and Test Conditions Table 66 — IDD0 Measurement-Loop Pattern Table 67 — IDD1 Measurement-Loop Pattern Table 68 — IDD4R Measurement-Loop Pattern Table 69 — IDD4W Measurement-Loop Pattern Table 70 — IDD7 Measurement-Loop Pattern Table 71 — AC Parameter Set for IDD Test Table 72 — Self Refresh Current Definitions 8.9 AC Timings Table 73 — AC Timings 8.10 Clock-to-Data Timing Sensitivity Table 74 — WCK-to-Data-In Timing Sensitivity Table 75 — WCK-to-Data-Out Timing Sensitivity 8.11 1.35 V I/O Driver Models Table 76 — 1.35 V I/O Impedances Figure 115 — Target Pull Down Characteristic at 40 Ohms Figure 116 — Target Pull Up/Termination Characteristic at 60 Ohms Figure 117 — Example of Non Linearity, Pull Down Characteristic at 40 Ohms Figure 118 — Example of Non Linearity, Pull Up/Termination Characteristic at 60 Ohms 8.12 1.25 V I/O Driver Models Table 77 — 1.25 V I/O Impedances Figure 119 — Target Pull Down Characteristic at 40 ohms Figure 120 — Target Pull Up/Termination Characteristic at 60 ohms Figure 121 — Example of Non Linearity, Pull Down Characteristic at 40 Ohms Figure 122 — Example of Non Linearity, Pull Up/Termination Characteristic at 60 Ohms 9 Package Specification 9.1 x32 Ball-out Figure 123 — x32 GDDR6 SGRAM 180-ball BGA Ball-out 9.2 x32 Package Outline Figure 124 — x32 Package Dimensions2 Table 78 — Package Parameters 9.3 x64 Ball-out Figure 125 — x64 GDDR6 SGRAM 460-ball BGA Ball-out 9.4 x64 Package Outline Figure 126 — x64 Package Dimensions2 Table 79 — x64 Package Parameters 9.5 Signals Table 80 — Ball-out Description 9.6 On Die Termination (ODT) Table 81 — Signals Affected by Termination Control Registers 9.7 x8 Mode Enable Figure 127 — Enabling x8 Mode Table 82 — x8 Mode (x32 Ball-out) Figure 128 — Example System View for x16 Mode vs. x8 Mode Figure 129 — Byte Orientation in Clamshell Topology (x32 Ball-out) Figure 130 — Example GDDR6 PCB Layout Topologies (x32 Ball-out) 9.8 Pseudo-channel (PC) Mode Table 83 — CAH Termination for CKE_n, CABI_n, CA[10:4] Table 84 — CAL Termination for CA[3:0] Table 85 — Example System Configuration for Pseudo-Channel Mode Figure 131 — Example System Configuration for Pseudo-Channel Mode 10 IEEE.1149.1 Boundary Scan 10.1 Test Pins Figure 132 — GDDR6 Dual TAP Controller Architecture 10.2 TAP Controller Figure 133 — TAP Controller 10.3 TAP Registers Figure 134 — Identification Register Figure 135 — Example Boundary Scan Cells Table 86 — Boundary Scan Register Bit Order 10.4 TAP Instruction Set Table 87 — Boundary Scan Instructions 10.5 Boundary Scan Operation Figure 136 — Example Boundary Scan Operation Table 88 — Boundary Scan AC Electrical Characteristics 10.6 Interactions Between Boundary Scan and Normal Device Operation 11 Annex A — (Informative) Differences between JESD250D and JESD250C Standard Improvement Form