راهنمای توسعه‌دهندگان نرم‌افزار معماری‌های Intel® ۶۴ و IA-۳۲، جلدهای ترکیبی: ۱، ۲A، ۲B، ۲C، ۲D، ۳A، ۳B، ۳C، ۳D و ۴

Volume 1:Basic Architecture Chapter 1 About This Manual 1.1 Intel® 64 and IA-32 Processors Covered in this Manual 1.2 Overview of Volume 1: Basic Architecture 1.3 Notational Conventions 1.3.1 Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility 1.3.2.1 Instruction Operands 1.3.3 Hexadecimal and Binary Numbers 1.3.4 Segmented Addressing 1.3.5 A New Syntax for CPUID, CR, and MSR Values 1.3.6 Exceptions 1.4 Related Literature Chapter 2 Intel® 64 and IA-32 Architectures 2.1 Brief History of Intel® 64 and IA-32 Architecture 2.1.1 16-bit Processors and Segmentation (1978) 2.1.2 The Intel® 286 Processor (1982) 2.1.3 The Intel386TM Processor (1985) 2.1.4 The Intel486TM Processor (1989) 2.1.5 The Intel® Pentium® Processor (1993) 2.1.6 The P6 Family of Processors (1995-1999) 2.1.7 The Intel® Pentium® 4 Processor Family (2000-2006) 2.1.8 The Intel® Xeon® Processor (2001- 2007) 2.1.9 The Intel® Pentium® M Processor (2003-2006) 2.1.10 The Intel® Pentium® Processor Extreme Edition (2005) 2.1.11 The Intel® CoreTM Duo and Intel® CoreTM Solo Processors (2006-2007) 2.1.12 The Intel® Xeon® Processor 5100, 5300 Series and Intel® CoreTM2 Processor Family (2006) 2.1.13 The Intel® Xeon® Processor 5200, 5400, 7400 Series and Intel® CoreTM2 Processor Family (2007) 2.1.14 The Intel® AtomTM Processor Family (2008) 2.1.15 The Intel® AtomTM Processor Family Based on Silvermont Microarchitecture (2013) 2.1.16 The Intel® CoreTMi7 Processor Family (2008) 2.1.17 The Intel® Xeon® Processor 7500 Series (2010) 2.1.18 2010 Intel® CoreTM Processor Family (2010) 2.1.19 The Intel® Xeon® Processor 5600 Series (2010) 2.1.20 The Second Generation Intel® CoreTM Processor Family (2011) 2.1.21 The Third Generation Intel® CoreTM Processor Family (2012) 2.1.22 The Fourth Generation Intel® CoreTM Processor Family (2013) 2.2 More on SPECIFIC advances 2.2.1 P6 Family Microarchitecture 2.2.2 Intel NetBurst® Microarchitecture 2.2.2.1 The Front End Pipeline 2.2.2.2 Out-Of-Order Execution Core 2.2.2.3 Retirement Unit 2.2.3 Intel® CoreTM Microarchitecture 2.2.3.1 The Front End 2.2.3.2 Execution Core 2.2.4 Intel® AtomTM Microarchitecture 2.2.5 Intel® Microarchitecture Code Name Nehalem 2.2.6 Intel® Microarchitecture Code Name Sandy Bridge 2.2.7 SIMD Instructions 2.2.8 Intel® Hyper-Threading Technology 2.2.8.1 Some Implementation Notes 2.2.9 Multi-Core Technology 2.2.10 Intel® 64 Architecture 2.2.11 Intel® Virtualization Technology (Intel® VT) 2.3 Intel® 64 and IA-32 processor generations 2.4 Proposed Removal of Intel Instruction Set ARchitecture and Features from Upcoming Products 2.5 Intel Instruction Set Architecture and Features Removed Chapter 3 Basic Execution Environment 3.1 Modes of Operation 3.1.1 Intel® 64 Architecture 3.2 Overview of the Basic Execution Environment 3.2.1 64-Bit Mode Execution Environment 3.3 Memory Organization 3.3.1 IA-32 Memory Models 3.3.2 Paging and Virtual Memory 3.3.3 Memory Organization in 64-Bit Mode 3.3.4 Modes of Operation vs. Memory Model 3.3.5 32-Bit and 16-Bit Address and Operand Sizes 3.3.6 Extended Physical Addressing in Protected Mode 3.3.7 Address Calculations in 64-Bit Mode 3.3.7.1 Canonical Addressing 3.4 Basic Program Execution Registers 3.4.1 General-Purpose Registers 3.4.1.1 General-Purpose Registers in 64-Bit Mode 3.4.2 Segment Registers 3.4.2.1 Segment Registers in 64-Bit Mode 3.4.3 EFLAGS Register 3.4.3.1 Status Flags 3.4.3.2 DF Flag 3.4.3.3 System Flags and IOPL Field 3.4.3.4 RFLAGS Register in 64-Bit Mode 3.5 Instruction Pointer 3.5.1 Instruction Pointer in 64-Bit Mode 3.6 Operand-Size and Address-Size Attributes 3.6.1 Operand Size and Address Size in 64-Bit Mode 3.7 Operand Addressing 3.7.1 Immediate Operands 3.7.2 Register Operands 3.7.2.1 Register Operands in 64-Bit Mode 3.7.3 Memory Operands 3.7.3.1 Memory Operands in 64-Bit Mode 3.7.4 Specifying a Segment Selector 3.7.4.1 Segmentation in 64-Bit Mode 3.7.5 Specifying an Offset 3.7.5.1 Specifying an Offset in 64-Bit Mode 3.7.6 Assembler and Compiler Addressing Modes 3.7.7 I/O Port Addressing Chapter 4 Data Types 4.1 Fundamental Data Types 4.1.1 Alignment of Words, Doublewords, Quadwords, and Double Quadwords 4.2 Numeric Data Types 4.2.1 Integers 4.2.1.1 Unsigned Integers 4.2.1.2 Signed Integers 4.2.2 Floating-Point Data Types 4.3 Pointer Data Types 4.3.1 Pointer Data Types in 64-Bit Mode 4.4 Bit Field Data Type 4.5 String Data Types 4.6 Packed SIMD Data Types 4.6.1 64-Bit SIMD Packed Data Types 4.6.2 128-Bit Packed SIMD Data Types 4.7 BCD and Packed BCD Integers 4.8 Real Numbers and Floating-Point Formats 4.8.1 Real Number System 4.8.2 Floating-Point Format 4.8.2.1 Normalized Numbers 4.8.2.2 Biased Exponent 4.8.3 Real Number and Non-number Encodings 4.8.3.1 Signed Zeros 4.8.3.2 Normalized and Denormalized Finite Numbers 4.8.3.3 Signed Infinities 4.8.3.4 NaNs 4.8.3.5 Operating on SNaNs and QNaNs 4.8.3.6 Using SNaNs and QNaNs in Applications 4.8.3.7 QNaN Floating-Point Indefinite 4.8.3.8 Half-Precision Floating-Point Operation 4.8.4 Rounding 4.8.4.1 Rounding Control (RC) Fields 4.8.4.2 Truncation with SSE and SSE2 Conversion Instructions 4.9 Overview of Floating-Point Exceptions 4.9.1 Floating-Point Exception Conditions 4.9.1.1 Invalid Operation Exception (#I) 4.9.1.2 Denormal Operand Exception (#D) 4.9.1.3 Divide-By-Zero Exception (#Z) 4.9.1.4 Numeric Overflow Exception (#O) 4.9.1.5 Numeric Underflow Exception (#U) 4.9.1.6 Inexact-Result (Precision) Exception (#P) 4.9.2 Floating-Point Exception Priority 4.9.3 Typical Actions of a Floating-Point Exception Handler Chapter 5 Instruction Set Summary 5.1 General-Purpose Instructions 5.1.1 Data Transfer Instructions 5.1.2 Binary Arithmetic Instructions 5.1.3 Decimal Arithmetic Instructions 5.1.4 Logical Instructions 5.1.5 Shift and Rotate Instructions 5.1.6 Bit and Byte Instructions 5.1.7 Control Transfer Instructions 5.1.8 String Instructions 5.1.9 I/O Instructions 5.1.10 Enter and Leave Instructions 5.1.11 Flag Control (EFLAG) Instructions 5.1.12 Segment Register Instructions 5.1.13 Miscellaneous Instructions 5.1.14 User Mode Extended Sate Save/Restore Instructions 5.1.15 Random Number Generator Instructions 5.1.16 BMI1, BMI2 5.1.16.1 Detection of VEX-encoded GPR Instructions, LZCNT and TZCNT, PREFETCHW 5.2 x87 FPU Instructions 5.2.1 x87 FPU Data Transfer Instructions 5.2.2 x87 FPU Basic Arithmetic Instructions 5.2.3 x87 FPU Comparison Instructions 5.2.4 x87 FPU Transcendental Instructions 5.2.5 x87 FPU Load Constants Instructions 5.2.6 x87 FPU Control Instructions 5.3 x87 FPU AND SIMD State Management Instructions 5.4 MMXTM Instructions 5.4.1 MMX Data Transfer Instructions 5.4.2 MMX Conversion Instructions 5.4.3 MMX Packed Arithmetic Instructions 5.4.4 MMX Comparison Instructions 5.4.5 MMX Logical Instructions 5.4.6 MMX Shift and Rotate Instructions 5.4.7 MMX State Management Instructions 5.5 SSE Instructions 5.5.1 SSE SIMD Single-Precision Floating-Point Instructions 5.5.1.1 SSE Data Transfer Instructions 5.5.1.2 SSE Packed Arithmetic Instructions 5.5.1.3 SSE Comparison Instructions 5.5.1.4 SSE Logical Instructions 5.5.1.5 SSE Shuffle and Unpack Instructions 5.5.1.6 SSE Conversion Instructions 5.5.2 SSE MXCSR State Management Instructions 5.5.3 SSE 64-Bit SIMD Integer Instructions 5.5.4 SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions 5.6 SSE2 Instructions 5.6.1 SSE2 Packed and Scalar Double-Precision Floating-Point Instructions 5.6.1.1 SSE2 Data Movement Instructions 5.6.1.2 SSE2 Packed Arithmetic Instructions 5.6.1.3 SSE2 Logical Instructions 5.6.1.4 SSE2 Compare Instructions 5.6.1.5 SSE2 Shuffle and Unpack Instructions 5.6.1.6 SSE2 Conversion Instructions 5.6.2 SSE2 Packed Single-Precision Floating-Point Instructions 5.6.3 SSE2 128-Bit SIMD Integer Instructions 5.6.4 SSE2 Cacheability Control and Ordering Instructions 5.7 SSE3 Instructions 5.7.1 SSE3 x87-FP Integer Conversion Instruction 5.7.2 SSE3 Specialized 128-bit Unaligned Data Load Instruction 5.7.3 SSE3 SIMD Floating-Point Packed ADD/SUB Instructions 5.7.4 SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions 5.7.5 SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions 5.7.6 SSE3 Agent Synchronization Instructions 5.8 Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions 5.8.1 Horizontal Addition/Subtraction 5.8.2 Packed Absolute Values 5.8.3 Multiply and Add Packed Signed and Unsigned Bytes 5.8.4 Packed Multiply High with Round and Scale 5.8.5 Packed Shuffle Bytes 5.8.6 Packed Sign 5.8.7 Packed Align Right 5.9 SSE4 Instructions 5.10 SSE4.1 Instructions 5.10.1 Dword Multiply Instructions 5.10.2 Floating-Point Dot Product Instructions 5.10.3 Streaming Load Hint Instruction 5.10.4 Packed Blending Instructions 5.10.5 Packed Integer MIN/MAX Instructions 5.10.6 Floating-Point Round Instructions with Selectable Rounding Mode 5.10.7 Insertion and Extractions from XMM Registers 5.10.8 Packed Integer Format Conversions 5.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks 5.10.10 Horizontal Search 5.10.11 Packed Test 5.10.12 Packed Qword Equality Comparisons 5.10.13 Dword Packing With Unsigned Saturation 5.11 SSE4.2 Instruction Set 5.11.1 String and Text Processing Instructions 5.11.2 Packed Comparison SIMD integer Instruction 5.12 AESNI and PCLMULQDQ 5.13 Intel® Advanced Vector Extensions (Intel® AVX) 5.14 16-bit Floating-Point Conversion 5.15 Fused-Multiply-ADD (FMA) 5.16 Intel® Advanced Vector Extensions 2 (Intel® AVX2) 5.17 Intel® Transactional Synchronization Extensions (Intel® TSX) 5.18 Intel® SHA Extensions 5.19 Intel® Advanced Vector Extensions 512 (Intel® AVX-512) 5.20 System Instructions 5.21 64-Bit Mode Instructions 5.22 Virtual-Machine Extensions 5.23 Safer Mode Extensions 5.24 Intel® Memory Protection Extensions 5.25 Intel® Software Guard Extensions Chapter 6 Procedure Calls, Interrupts, and Exceptions 6.1 Procedure Call Types 6.2 Stacks 6.2.1 Setting Up a Stack 6.2.2 Stack Alignment 6.2.3 Address-Size Attributes for Stack Accesses 6.2.4 Procedure Linking Information 6.2.4.1 Stack-Frame Base Pointer 6.2.4.2 Return Instruction Pointer 6.2.5 Stack Behavior in 64-Bit Mode 6.3 Calling Procedures Using CALL and RET 6.3.1 Near CALL and RET Operation 6.3.2 Far CALL and RET Operation 6.3.3 Parameter Passing 6.3.3.1 Passing Parameters Through the General-Purpose Registers 6.3.3.2 Passing Parameters on the Stack 6.3.3.3 Passing Parameters in an Argument List 6.3.4 Saving Procedure State Information 6.3.5 Calls to Other Privilege Levels 6.3.6 CALL and RET Operation Between Privilege Levels 6.3.7 Branch Functions in 64-Bit Mode 6.4 Interrupts and Exceptions 6.4.1 Call and Return Operation for Interrupt or Exception Handling Procedures 6.4.2 Calls to Interrupt or Exception Handler Tasks 6.4.3 Interrupt and Exception Handling in Real-Address Mode 6.4.4 INT n, INTO, INT3, INT1, and BOUND Instructions 6.4.5 Handling Floating-Point Exceptions 6.4.6 Interrupt and Exception Behavior in 64-Bit Mode 6.5 Procedure Calls for Block-Structured Languages 6.5.1 ENTER Instruction 6.5.2 LEAVE Instruction Chapter 7 Programming With General-Purpose Instructions 7.1 Programming environment for GP Instructions 7.2 Programming Environment for GP Instructions in 64-Bit Mode 7.3 Summary of GP Instructions 7.3.1 Data Transfer Instructions 7.3.1.1 General Data Movement Instructions 7.3.1.2 Exchange Instructions 7.3.1.3 Exchange Instructions in 64-Bit Mode 7.3.1.4 Stack Manipulation Instructions 7.3.1.5 Stack Manipulation Instructions in 64-Bit Mode 7.3.1.6 Type Conversion Instructions 7.3.1.7 Type Conversion Instructions in 64-Bit Mode 7.3.2 Binary Arithmetic Instructions 7.3.2.1 Addition and Subtraction Instructions 7.3.2.2 Increment and Decrement Instructions 7.3.2.3 Increment and Decrement Instructions in 64-Bit Mode 7.3.2.4 Comparison and Sign Change Instructions 7.3.2.5 Multiplication and Division Instructions 7.3.3 Decimal Arithmetic Instructions 7.3.3.1 Packed BCD Adjustment Instructions 7.3.3.2 Unpacked BCD Adjustment Instructions 7.3.4 Decimal Arithmetic Instructions in 64-Bit Mode 7.3.5 Logical Instructions 7.3.6 Shift and Rotate Instructions 7.3.6.1 Shift Instructions 7.3.6.2 Double-Shift Instructions 7.3.6.3 Rotate Instructions 7.3.7 Bit and Byte Instructions 7.3.7.1 Bit Test and Modify Instructions 7.3.7.2 Bit Scan Instructions 7.3.7.3 Byte Set on Condition Instructions 7.3.7.4 Test Instruction 7.3.8 Control Transfer Instructions 7.3.8.1 Unconditional Transfer Instructions 7.3.8.2 Conditional Transfer Instructions 7.3.8.3 Control Transfer Instructions in 64-Bit Mode 7.3.8.4 Software Interrupt Instructions 7.3.8.5 Software Interrupt Instructions in 64-bit Mode and Compatibility Mode 7.3.9 String Operations 7.3.9.1 String Instructions 7.3.9.2 Repeated String Operations 7.3.9.3 Fast-String Operation 7.3.9.4 String Operations in 64-Bit Mode 7.3.10 I/O Instructions 7.3.11 I/O Instructions in 64-Bit Mode 7.3.12 Enter and Leave Instructions 7.3.13 Flag Control (EFLAG) Instructions 7.3.13.1 Carry and Direction Flag Instructions 7.3.13.2 EFLAGS Transfer Instructions 7.3.13.3 Interrupt Flag Instructions 7.3.14 Flag Control (RFLAG) Instructions in 64-Bit Mode 7.3.15 Segment Register Instructions 7.3.15.1 Segment-Register Load and Store Instructions 7.3.15.2 Far Control Transfer Instructions 7.3.15.3 Software Interrupt Instructions 7.3.15.4 Load Far Pointer Instructions 7.3.16 Miscellaneous Instructions 7.3.16.1 Address Computation Instruction 7.3.16.2 Table Lookup Instructions 7.3.16.3 Processor Identification Instruction 7.3.16.4 No-Operation and Undefined Instructions 7.3.17 Random Number Generator Instructions 7.3.17.1 RDRAND 7.3.17.2 RDSEED Chapter 8 Programming with the x87 FPU 8.1 x87 FPU Execution Environment 8.1.1 x87 FPU in 64-Bit Mode and Compatibility Mode 8.1.2 x87 FPU Data Registers 8.1.2.1 Parameter Passing With the x87 FPU Register Stack 8.1.3 x87 FPU Status Register 8.1.3.1 Top of Stack (TOP) Pointer 8.1.3.2 Condition Code Flags 8.1.3.3 x87 FPU Floating-Point Exception Flags 8.1.3.4 Stack Fault Flag 8.1.4 Branching and Conditional Moves on Condition Codes 8.1.5 x87 FPU Control Word 8.1.5.1 x87 FPU Floating-Point Exception Mask Bits 8.1.5.2 Precision Control Field 8.1.5.3 Rounding Control Field 8.1.6 Infinity Control Flag 8.1.7 x87 FPU Tag Word 8.1.8 x87 FPU Instruction and Data (Operand) Pointers 8.1.9 Last Instruction Opcode 8.1.9.1 Fopcode Compatibility Sub-mode 8.1.10 Saving the x87 FPU’s State with FSTENV/FNSTENV and FSAVE/FNSAVE 8.1.11 Saving the x87 FPU’s State with FXSAVE 8.2 x87 FPU Data Types 8.2.1 Indefinites 8.2.2 Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals 8.3 x87 FPU Instruction Set 8.3.1 Escape (ESC) Instructions 8.3.2 x87 FPU Instruction Operands 8.3.3 Data Transfer Instructions 8.3.4 Load Constant Instructions 8.3.5 Basic Arithmetic Instructions 8.3.6 Comparison and Classification Instructions 8.3.6.1 Branching on the x87 FPU Condition Codes 8.3.7 Trigonometric Instructions 8.3.8 Approximation of Pi 8.3.9 Logarithmic, Exponential, and Scale 8.3.10 Transcendental Instruction Accuracy 8.3.11 x87 FPU Control Instructions 8.3.12 Waiting vs. Non-waiting Instructions 8.3.13 Unsupported x87 FPU Instructions 8.4 x87 FPU Floating-Point Exception Handling 8.4.1 Arithmetic vs. Non-arithmetic Instructions 8.5 x87 FPU Floating-Point Exception Conditions 8.5.1 Invalid Operation Exception 8.5.1.1 Stack Overflow or Underflow Exception (#IS) 8.5.1.2 Invalid Arithmetic Operand Exception (#IA) 8.5.2 Denormal Operand Exception (#D) 8.5.3 Divide-By-Zero Exception (#Z) 8.5.4 Numeric Overflow Exception (#O) 8.5.5 Numeric Underflow Exception (#U) 8.5.6 Inexact-Result (Precision) Exception (#P) 8.6 x87 FPU Exception Synchronization 8.7 Handling x87 FPU Exceptions in Software 8.7.1 Native Mode 8.7.2 MS-DOS* Compatibility Sub-mode 8.7.3 Handling x87 FPU Exceptions in Software Chapter 9 Programming with Intel® MMXTM Technology 9.1 Overview of MMX Technology 9.2 The MMX Technology Programming Environment 9.2.1 MMX Technology in 64-Bit Mode and Compatibility Mode 9.2.2 MMX Registers 9.2.3 MMX Data Types 9.2.4 Memory Data Formats 9.2.5 Single Instruction, Multiple Data (SIMD) Execution Model 9.3 Saturation and Wraparound Modes 9.4 MMX Instructions 9.4.1 Data Transfer Instructions 9.4.2 Arithmetic Instructions 9.4.3 Comparison Instructions 9.4.4 Conversion Instructions 9.4.5 Unpack Instructions 9.4.6 Logical Instructions 9.4.7 Shift Instructions 9.4.8 EMMS Instruction 9.5 Compatibility with x87 FPU Architecture 9.5.1 MMX Instructions and the x87 FPU Tag Word 9.6 WRITING APPLICATIONS WITH MMX CODE 9.6.1 Checking for MMX Technology Support 9.6.2 Transitions Between x87 FPU and MMX Code 9.6.3 Using the EMMS Instruction 9.6.4 Mixing MMX and x87 FPU Instructions 9.6.5 Interfacing with MMX Code 9.6.6 Using MMX Code in a Multitasking Operating System Environment 9.6.7 Exception Handling in MMX Code 9.6.8 Register Mapping 9.6.9 Effect of Instruction Prefixes on MMX Instructions Chapter 10 Programming with Intel® Streaming SIMD Extensions (Intel® SSE) 10.1 Overview of SSE Extensions 10.2 SSE Programming Environment 10.2.1 SSE in 64-Bit Mode and Compatibility Mode 10.2.2 XMM Registers 10.2.3 MXCSR Control and Status Register 10.2.3.1 SIMD Floating-Point Mask and Flag Bits 10.2.3.2 SIMD Floating-Point Rounding Control Field 10.2.3.3 Flush-To-Zero 10.2.3.4 Denormals-Are-Zeros 10.2.4 Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU 10.3 SSE Data Types 10.4 SSE Instruction Set 10.4.1 SSE Packed and Scalar Floating-Point Instructions 10.4.1.1 SSE Data Movement Instructions 10.4.1.2 SSE Arithmetic Instructions 10.4.2 SSE Logical Instructions 10.4.2.1 SSE Comparison Instructions 10.4.2.2 SSE Shuffle and Unpack Instructions 10.4.3 SSE Conversion Instructions 10.4.4 SSE 64-Bit SIMD Integer Instructions 10.4.5 MXCSR State Management Instructions 10.4.6 Cacheability Control, Prefetch, and Memory Ordering Instructions 10.4.6.1 Cacheability Control Instructions 10.4.6.2 Caching of Temporal vs. Non-Temporal Data 10.4.6.3 PREFETCHh Instructions 10.4.6.4 SFENCE Instruction 10.5 FXSAVE and FXRSTOR Instructions 10.5.1 FXSAVE Area 10.5.1.1 x87 State 10.5.1.2 SSE State 10.5.2 Operation of FXSAVE 10.5.3 Operation of FXRSTOR 10.6 Handling SSE Instruction Exceptions 10.7 Writing Applications with the SSE Extensions Chapter 11 Programming with Intel® Streaming SIMD Extensions 2 (Intel® SSE2) 11.1 Overview of SSE2 Extensions 11.2 SSE2 Programming Environment 11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode 11.2.2 Compatibility of SSE2 Extensions with SSE, MMX Technology and x87 FPU Programming Environment 11.2.3 Denormals-Are-Zeros Flag 11.3 SSE2 Data Types 11.4 SSE2 Instructions 11.4.1 Packed and Scalar Double-Precision Floating-Point Instructions 11.4.1.1 Data Movement Instructions 11.4.1.2 SSE2 Arithmetic Instructions 11.4.1.3 SSE2 Logical Instructions 11.4.1.4 SSE2 Comparison Instructions 11.4.1.5 SSE2 Shuffle and Unpack Instructions 11.4.1.6 SSE2 Conversion Instructions 11.4.2 SSE2 64-Bit and 128-Bit SIMD Integer Instructions 11.4.3 128-Bit SIMD Integer Instruction Extensions 11.4.4 Cacheability Control and Memory Ordering Instructions 11.4.4.1 FLUSH Cache Line 11.4.4.2 Cacheability Control Instructions 11.4.4.3 Memory Ordering Instructions 11.4.4.4 Pause 11.4.5 Branch Hints 11.5 SSE, SSE2, and SSE3 Exceptions 11.5.1 SIMD Floating-Point Exceptions 11.5.2 SIMD Floating-Point Exception Conditions 11.5.2.1 Invalid Operation Exception (#I) 11.5.2.2 Denormal-Operand Exception (#D) 11.5.2.3 Divide-By-Zero Exception (#Z) 11.5.2.4 Numeric Overflow Exception (#O) 11.5.2.5 Numeric Underflow Exception (#U) 11.5.2.6 Inexact-Result (Precision) Exception (#P) 11.5.3 Generating SIMD Floating-Point Exceptions 11.5.3.1 Handling Masked Exceptions 11.5.3.2 Handling Unmasked Exceptions 11.5.3.3 Handling Combinations of Masked and Unmasked Exceptions 11.5.4 Handling SIMD Floating-Point Exceptions in Software 11.5.5 Interaction of SIMD and x87 FPU Floating-Point Exceptions 11.6 Writing Applications with SSE/SSE2 Extensions 11.6.1 General Guidelines for Using SSE/SSE2 Extensions 11.6.2 Checking for SSE/SSE2 Support 11.6.3 Checking for the DAZ Flag in the MXCSR Register 11.6.4 Initialization of SSE/SSE2 Extensions 11.6.5 Saving and Restoring the SSE/SSE2 State 11.6.6 Guidelines for Writing to the MXCSR Register 11.6.7 Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions 11.6.8 Compatibility of SIMD and x87 FPU Floating-Point Data Types 11.6.9 Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and Data 11.6.10 Interfacing with SSE/SSE2 Procedures and Functions 11.6.10.1 Passing Parameters in XMM Registers 11.6.10.2 Saving XMM Register State on a Procedure or Function Call 11.6.10.3 Caller-Save Recommendation for Procedure and Function Calls 11.6.11 Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions 11.6.12 Branching on Arithmetic Operations 11.6.13 Cacheability Hint Instructions 11.6.14 Effect of Instruction Prefixes on the SSE/SSE2 Instructions Chapter 12 Programming with Intel® SSE3, SSSE3, Intel® SSE4 and Intel® AESNI 12.1 Programming Environment and Data types 12.1.1 SSE3, SSSE3, SSE4 in 64-Bit Mode and Compatibility Mode 12.1.2 Compatibility of SSE3/SSSE3 with MMX Technology, the x87 FPU Environment, and SSE/SSE2 Extensions 12.1.3 Horizontal and Asymmetric Processing 12.2 Overview of SSE3 Instructions 12.3 SSE3 Instructions 12.3.1 x87 FPU Instruction for Integer Conversion 12.3.2 SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load 12.3.3 SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE Performance 12.3.4 SIMD Floating-Point Instructions Provide Packed Addition/Subtraction 12.3.5 SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction 12.3.6 Two Thread Synchronization Instructions 12.4 Writing Applications with SSE3 Extensions 12.4.1 Guidelines for Using SSE3 Extensions 12.4.2 Checking for SSE3 Support 12.4.3 Enable FTZ and DAZ for SIMD Floating-Point Computation 12.4.4 Programming SSE3 with SSE/SSE2 Extensions 12.5 Overview of SSSE3 Instructions 12.6 SSSE3 Instructions 12.6.1 Horizontal Addition/Subtraction 12.6.2 Packed Absolute Values 12.6.3 Multiply and Add Packed Signed and Unsigned Bytes 12.6.4 Packed Multiply High with Round and Scale 12.6.5 Packed Shuffle Bytes 12.6.6 Packed Sign 12.6.7 Packed Align Right 12.7 Writing Applications with SSSE3 Extensions 12.7.1 Guidelines for Using SSSE3 Extensions 12.7.2 Checking for SSSE3 Support 12.8 SSE3/SSSE3 And SSE4 Exceptions 12.8.1 Device Not Available (DNA) Exceptions 12.8.2 Numeric Error flag and IGNNE# 12.8.3 Emulation 12.8.4 IEEE 754 Compliance of SSE4.1 Floating-Point Instructions 12.9 SSE4 Overview 12.10 SSE4.1 Instruction Set 12.10.1 Dword Multiply Instructions 12.10.2 Floating-Point Dot Product Instructions 12.10.3 Streaming Load Hint Instruction 12.10.4 Packed Blending Instructions 12.10.5 Packed Integer MIN/MAX Instructions 12.10.6 Floating-Point Round Instructions with Selectable Rounding Mode 12.10.7 Insertion and Extractions from XMM Registers 12.10.8 Packed Integer Format Conversions 12.10.9 Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks 12.10.10 Horizontal Search 12.10.11 Packed Test 12.10.12 Packed Qword Equality Comparisons 12.10.13 Dword Packing With Unsigned Saturation 12.11 SSE4.2 Instruction Set 12.11.1 String and Text Processing Instructions 12.11.1.1 Memory Operand Alignment 12.11.2 Packed Comparison SIMD Integer Instruction 12.12 Writing Applications with SSE4 Extensions 12.12.1 Guidelines for Using SSE4 Extensions 12.12.2 Checking for SSE4.1 Support 12.12.3 Checking for SSE4.2 Support 12.13 AESNI Overview 12.13.1 Little-Endian Architecture and Big-Endian Specification (FIPS 197) 12.13.1.1 AES Data Structure in Intel 64 Architecture 12.13.2 AES Transformations and Functions 12.13.3 PCLMULQDQ 12.13.4 Checking for AESNI Support Chapter 13 Managing State Using the XSAVE Feature Set 13.1 XSAVE-Supported Features and State-Component Bitmaps 13.2 Enumeration of CPU Support for XSAVE Instructions and XSAVE- Supported Features 13.3 Enabling the XSAVE Feature Set and XSAVE-Enabled Features 13.4 XSAVE Area 13.4.1 Legacy Region of an XSAVE Area 13.4.2 XSAVE Header 13.4.3 Extended Region of an XSAVE Area 13.5 XSAVE-Managed State 13.5.1 x87 State 13.5.2 SSE State 13.5.3 AVX State 13.5.4 MPX State 13.5.5 AVX-512 State 13.5.6 PT State 13.5.7 PKRU State 13.5.8 HDC State 13.6 Processor Tracking of XSAVE-Managed State 13.7 Operation of XSAVE 13.8 Operation of XRSTOR 13.8.1 Standard Form of XRSTOR 13.8.2 Compacted Form of XRSTOR 13.8.3 XRSTOR and the Init and Modified Optimizations 13.9 Operation of XSAVEOPT 13.10 Operation of XSAVEC 13.11 Operation of XSAVES 13.12 Operation of XRSTORS 13.13 Memory Accesses by the XSAVE Feature Set Chapter 14 Programming with AVX, FMA and AVX2 14.1 Intel AVX Overview 14.1.1 256-Bit Wide SIMD Register Support 14.1.2 Instruction Syntax Enhancements 14.1.3 VEX Prefix Instruction Encoding Support 14.2 Functional Overview 14.2.1 256-bit Floating-Point Arithmetic Processing Enhancements 14.2.2 256-bit Non-Arithmetic Instruction Enhancements 14.2.3 Arithmetic Primitives for 128-bit Vector and Scalar processing 14.2.4 Non-Arithmetic Primitives for 128-bit Vector and Scalar Processing 14.3 Detection of AVX Instructions 14.3.1 Detection of VEX-Encoded AES and VPCLMULQDQ 14.4 Half-Precision Floating-Point Conversion 14.4.1 Detection of F16C Instructions 14.5 Fused-Multiply-ADD (FMA) Extensions 14.5.1 FMA Instruction Operand Order and Arithmetic Behavior 14.5.2 Fused-Multiply-ADD (FMA) Numeric Behavior 14.5.3 Detection of FMA 14.6 Overview of Intel® Advanced Vector Extensions 2 (Intel® AVX2) 14.6.1 AVX2 and 256-bit Vector Integer Processing 14.7 Promoted Vector Integer Instructions in AVX2 14.7.1 Detection of AVX2 14.8 Accessing YMM Registers 14.9 Memory alignment 14.10 SIMD floating-point ExCeptions 14.11 Emulation 14.12 Writing AVX floating-point exception handlers 14.13 General Purpose Instruction Set Enhancements Chapter 15 Programming with Intel® AVX-512 15.1 Overview 15.1.1 512-Bit Wide SIMD Register Support 15.1.2 32 SIMD Register Support 15.1.3 Eight Opmask Register Support 15.1.4 Instruction Syntax Enhancement 15.1.5 EVEX Instruction Encoding Support 15.2 Detection of AVX-512 Foundation Instructions 15.2.1 Additional 512-bit Instruction Extensions of the Intel AVX-512 Family 15.3 Detection of 512-bit Instruction Groups of Intel® AVX-512 Family 15.4 Detection of Intel AVX-512 Instruction Groups Operating at 256 and 128-bit Vector Lengths 15.5 Accessing XMM, YMM AND ZMM Registers 15.6 Enhanced Vector Programming Environment Using EVEX Encoding 15.6.1 OPMASK Register to Predicate Vector Data Processing 15.6.1.1 Opmask Register K0 15.6.1.2 Example of Opmask Usages 15.6.2 OpMask Instructions 15.6.3 Broadcast 15.6.4 Static Rounding Mode and Suppress All Exceptions 15.6.5 Compressed Disp8*N Encoding 15.7 Memory Alignment 15.8 SIMD Floating-Point Exceptions 15.9 Instruction Exception Specification 15.10 Emulation 15.11 Writing floating-point exception handlers Chapter 16 Programming with Intel® Transactional Synchronization Extensions 16.1 Overview 16.2 Intel® Transactional Synchronization Extensions 16.2.1 HLE Software Interface 16.2.2 RTM Software Interface 16.3 Intel® TSX Application Programming Model 16.3.1 Detection of Transactional Synchronization Support 16.3.1.1 Detection of HLE Support 16.3.1.2 Detection of RTM Support 16.3.1.3 Detection of XTEST Instruction 16.3.2 Querying Transactional Execution Status 16.3.3 Requirements for HLE Locks 16.3.4 Transactional Nesting 16.3.4.1 HLE Nesting and Elision 16.3.4.2 RTM Nesting 16.3.4.3 Nesting HLE and RTM 16.3.5 RTM Abort Status Definition 16.3.6 RTM Memory Ordering 16.3.7 RTM-Enabled Debugger Support 16.3.8 Programming Considerations 16.3.8.1 Instruction Based Considerations 16.3.8.2 Runtime Considerations Chapter 17 Intel® Memory Protection Extensions 17.1 Intel® Memory Protection Extensions (Intel® MPX) 17.2 Introduction 17.3 Intel MPX Programming Environment 17.3.1 Detection and Enumeration of Intel MPX Interfaces 17.3.2 Bounds Registers 17.3.3 Configuration and Status Registers 17.3.4 Read and Write of IA32_BNDCFGS 17.4 Intel MPX Instruction Summary 17.4.1 Instruction Encoding 17.4.2 Usage and Examples 17.4.3 Loading and Storing Bounds in Memory 17.4.3.1 BNDLDX and BNDSTX in 64-Bit Mode 17.4.3.2 BNDLDX and BNDSTX Outside 64-Bit Mode 17.5 Interactions with Intel MPX 17.5.1 Intel MPX and Operating Modes 17.5.2 Intel MPX Support for Pointer Operations with Branching 17.5.3 CALL, RET, JMP and All Jcc 17.5.4 BOUND Instruction and Intel MPX 17.5.5 Programming Considerations 17.5.6 Intel MPX and System Management Mode 17.5.7 Support of Intel MPX in VMCS 17.5.8 Support of Intel MPX in Intel TSX Chapter 18 Input/Output 18.1 I/O Port Addressing 18.2 I/O Port Hardware 18.3 I/O Address Space 18.3.1 Memory-Mapped I/O 18.4 I/O Instructions 18.5 Protected-Mode I/O 18.5.1 I/O Privilege Level 18.5.2 I/O Permission Bit Map 18.6 Ordering I/O Chapter 19 Processor Identification and Feature Determination 19.1 Using the CPUID Instruction 19.1.1 Notes on Where to Start 19.1.2 Identification of Earlier IA-32 Processors Appendix A EFLAGS Cross-Reference A.1 EFLAGS and Instructions Appendix B EFLAGS Condition Codes B.1 Condition Codes Appendix C Floating-Point Exceptions Summary C.1 Overview C.2 x87 FPU Instructions C.3 SSE Instructions C.4 SSE2 Instructions C.5 SSE3 Instructions C.6 SSSE3 Instructions C.7 SSE4 Instructions Appendix D Guidelines for Writing x87 FPU Exception Handlers D.1 MS-DOS Compatibility Sub-mode for Handling x87 FPU Exceptions D.2 Implementation of the MS-DOS* Compatibility Sub-mode in the Intel486TM, Pentium®, and P6 Processor Family, and Pentium® 4 Processors D.2.1 MS-DOS* Compatibility Sub-mode in the Intel486TM and Pentium® Processors D.2.1.1 Basic Rules: When FERR# Is Generated D.2.1.2 Recommended External Hardware to Support the MS-DOS* Compatib