Integrated circuit and system design : power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 : revised selected papers

"This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008." "The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures."--Back cover Front Matter....Pages - Subthreshold FIR Filter Architecture for Ultra Low Power Applications....Pages 1-10 Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs....Pages 11-20 Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits....Pages 21-30 Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction....Pages 31-41 Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating....Pages 42-51 Intelligate: Scalable Dynamic Invariant Learning for Power Reduction....Pages 52-61 Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption....Pages 62-71 Power-Aware Design via Micro-architectural Link to Implementation....Pages 72-81 Untraditional Approach to Computer Energy Reduction....Pages 82-92 Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication....Pages 93-102 Power Optimization of Parallel Multipliers in Systems with Variable Word-Length....Pages 103-115 A Design Space Comparison of 6T and 8T SRAM Core-Cells....Pages 116-125 Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization....Pages 126-135 Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic....Pages 136-145 A Study on CMOS Time Uncertainty with Technology Scaling....Pages 146-155 Static Timing Model Extraction for Combinational Circuits....Pages 156-166 A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA....Pages 167-177 Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power....Pages 178-187 Logic Synthesis of Handshake Components Using Structural Clustering Techniques....Pages 188-198 Fast Universal Synchronizers....Pages 199-208 A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router....Pages 209-218 PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels....Pages 219-228 Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits....Pages 229-236 A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint....Pages 237-246 Generating Worst-Case Stimuli for Accurate Power Grid Analysis....Pages 247-257 Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization....Pages 258-267 Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements....Pages 268-276 A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation....Pages 277-286 Energy Efficient Elliptic Curve Processor....Pages 287-296 Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing....Pages 297-306 Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures....Pages 307-317 Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers....Pages 318-327 Ultra Low Voltage High Speed Differential CMOS Inverter....Pages 328-337 Differential Capacitance Analysis....Pages 338-347 Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey....Pages 348-358 Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses....Pages 359-368 Analytical High-Level Power Model for LUT-Based Components....Pages 369-378 A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption....Pages 379-388 Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates....Pages 389-398 Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level....Pages 399-408 Data Dependence of Delay Distribution for a Planar Bus....Pages 409-418 Towards Novel Approaches in Design Automation for FPGA Power Optimization....Pages 419-428 Smart Enumeration: A Systematic Approach to Exhaustive Search....Pages 429-438 An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs....Pages 439-448 Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor....Pages 449-457 Integration of Power Management Units onto the SoC....Pages 458-458 Model to Hardware Matching for nm Scale Technologies....Pages 459-459 Power and Profit: Engineering in the Envelope....Pages 460-460 Back Matter....Pages - Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.