Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 17th International Workshop, PATMOS 2007, Gothenburg, ... (Lecture Notes in Computer Science, 4644)

th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript. Title Page Preface Organization Table of Contents System-Level Application-Specific NoC Design for Network and Multimedia Applications Introduction Related Work NoC Design Methodology and Simulator Description NoC Design Methodology NoC Simulator Description Experimental Results Methodology Applied to Multimedia Applications Methodology Applied to Network Application Conclusion References Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements Introduction Related Works Model Construction Basics Model Structure and Parameters Model Construction Case Study Methodology Application Model Validation Conclusion References A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms Introduction Definitions-Notation Architectural - Functional Overview Analysis Case Studies Image Filtering Combinatorial Optimization in Hardware/Software Codesign Conclusion References An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture Introduction Context Platform Description Formulation Problem TheDesignFlow 4G Radio Communication Application 4G Context Specification IP Block Model Simulation Results Simulation Exploration Methodology Simulation Results Conclusion and Future Works References Template Vertical Dictionary-Based Program Compression Scheme on the TTA Introduction Transport Triggered Architecture Code Characteristics Analysis Code Compression Algorithm Template-Based Compression Vertical Dictionary-Based Compression Hardware Prototype Experiments Compression Ratio Area and Power Consumption Conclusions References Asynchronous Functional Coupling for Low Power Sensor Network Processors Introduction Low Power Design Techniques TI MSP 430 Microprocessor Asynchronous SN Processor Implementation Comparison References A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs Introduction Preliminaries Cyclic Graph Model Retiming Valid Periodic Schedule Problem Description and Proposed Resolution Approach Experimental Results Conclusions References Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports Introduction 12T CAM Cell Cell Structure Cell Layout Design Topology Architectural Overview Functional Overview Simulation and Results Conclusion References The Design and Implementation of a Power Efficient Embedded SRAM Introduction Low-Swing Write Techniques Dual-Rail Decoder Architecture and Timing Experimental Results Conclusions References Design of a Linear Power Amplifier with ±1.5V PowerSupply Using ALADIN Introduction Novel ALADIN Tools Modified Calculation of Current Density Heat Simulation Design of the Linear Power Amplifier Layout Solutions Simulation Results Conclusions References Settling Time Minimization of Operational Amplifiers Introduction Minimization of Settling Time of a Generic Op-amp First Order Response Second Order Response Third Order Response Application Example Conclusions and Future Work References Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs Introduction Theoretical Analysis The Temperature Behavior of the New CMOS Weak Inversion Bandgap Reference The Implementation of the CT 0.5 Block Low-Power Operation Bandgap Reference Using DTMOSTs The Implementation of PTAT Voltage Generator Using $\OVF$ (OffsetVoltage Follower) Block CMOS Implementation of the Low-Voltage Low-Power Weak Inversion DTMOST Bandgap Reference Experimental Results Conclusions References Computation of Joint Timing Yield of Sequential Networks Considering Process Variations Introduction Characterization of Flip Flops Models for Flip-Flop Parameters Timing Yield of Sequential Networks SSTA of Combinational Circuits Clock Skew Analysis Timing Constraints Joint Timing Yield Estimation Experimental Results Conclusions References A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation Introduction Statistical Timing Analysis Flow Standard Cell Characterization Timing Analyzer $Core$ Validation Monte Carlo vs. Statistically Calculated Values Statistically Calculated Values vs. Silicon Data Timing Margins and Improved SSTA Flow Conclusion References A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits Introduction Preliminaries Statistical Timing Models and Analysis Timing Yield of Sequential Circuits Timing Yield and Register Configuration Timing Yield Changed by Latch Replacement Problem Formulation Statistical Latch Replacement Optimization Flow Overview Statistical Dynamic Programming Experimental Results Conclusions and Future Work References A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect Introduction NBTI Model Previous NBTI Models Our Novel Gate-Level NBTI Model with Stacking Effect Gate-Level Delay Degradation Analysis Traditional Gate DelayModel Our Novel Gate-Level Delay Model Experimental Results Conclusion References Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components Introduction Related Work Gate Level Model Inverter Model Modelling Other Gates Also Considering Temperature and Load ExtensiontoRTLevel Modelling the Critical Path of an RT Component Varying Critical Paths Evaluation Conclusion References Logic Style Comparison for Ultra Low Power Operation in 65nm Technology Introduction Logic Families Selection for Design Comparison Previous Work Selected Logic Families Multi-threshold Complementary Pass-Gate Logic (MTCPL) for Ultra Low Voltage Operation Basic Concept Delay Analysis Proposed Changes for Ultra Low Power Operation Setup and Experimental Procedure Ultra Low-Power Performance Conclusion References Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation Introduction Modeling of HCI and NBTI Degradation HCI in NMOS NBTI Modeling Reliability Simulation Silicon Verification Analysis of Circuits Conclusions References Clock Distribution Techniques for Low-EMI Design Introduction EMI in Digital Design: Previous Work Spectral Analysis of Digital Signals Clock Distribution Techniques for EMC-Aware Design Clock-Tree Synthesi\s for Low EMI Clock Skew for Low EMI Experimental Results Conclusions References Crosstalk Waveform Modeling Using Wave Fitting Introduction Methodology Overview Other Analytical Models Trapezoid Waveform Isosceles Triangular Wave Model Weibull Wave Model Comprehensive Waveform Set Generation Reference Waveform Set Waveform Transformation Error Matrix Generation Noise Analysis with Wave Fitting References Weakness Identification for Effective Repair of Power Distribution Network Introduction PDN Weakness Identification and Fixing Problem Issues in PDN Fixing Assumption and Problem Formulation Solving a PDN Fixing Problem PDNWeakness Identification: Box-Scan Search Voltage Recovery Estimation Simulation Examples Conclusion References New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses Introduction Adaptive Encoding Schemes for Activity Balancing Coarse-Grained Balancing Scheme Fine-Grained Balancing Scheme Codec Architecture Experimental Results Experimental Set-Up Parameter Space Exploration Experimental Data Conclusions References On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects Introduction Delay and Transition Activity in VDSM Interconnects Improving Throughput and Power in Buses by Coding Coding and Classic Anti-crosstalk Techniques Simple Coding Schemes for Improving Throughput Spacing and Shielding Combining Coding with Spacing and Shielding Combining Coding with Spacing Optimizing Delay and Transition Activity Optimizing Delay and Total Transition Activity Concluding Remarks References Soft Error-Aware Power Optimization Using Gate Sizing Introduction Preliminaries Power and Delay Models Single Event Upset System Lifetime and MTTF Statistical Analysis of Gate Masking General Approach Reliability of Results Problem Formulation Convexity of the Optimization Problem Simulation Results Conclusion References Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices Introduction Related Work Characterization Tool Measurement Circuit Energy Model Optimization System GCC RTL Representation Optimization Algorithms Evaluation and Results Measurement Circuit Optimization System Conclusion References RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating Introduction Related Work Modeling of Power Gating Modeling the On-State Modeling the Off-State Modeling the Switch-Over Estimation Framework ModelEvaluation Estimation Flow Evaluation Conclusion References Functional Verification of Low Power Designs at RTL Introduction Power Management Techniques Power Management Design Structure Retention Memory Elements Specifying Design Intent of Low Power Designs Power Aware Simulation PA Simulation Flow Register, Latch, and Memory Recognition Identification of Power Elements Elaborating the Power Aware Design Power Aware Simulation Example Sample Design Power Configuration File For Further Investigation Conclusion References XEEMU: An Improved XScale Power Simulator Introduction Related Work XTREM – An In-Depth Review Experimental Setup and Benchmarks Performance Validation Power Modeling Experimental Results Conclusions and Future Work References Low Power Elliptic Curve Cryptography Introduction Characteristic 2 Finite Fields Elliptic Curves Coordinate System Point Scalar Multiplication Algorithms Hardware Implementation $GF(2^m)$ Components Reconfigurable Elliptic Curve Processor Results Conclusions References Design and Test of Self-checking AsynchronousControl Circuit Introduction Background Labeled Petri Ne Direct Mapping Fail-Stop David Cell Design and Test of Self-checking Asynchronous Circuits Linear Structure Fork/Join Structure Merge/Choice Structure Conclusion and Future Work References An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips Introduction Motivation QDI Asynchronous Circuits Persia: A Synthesis Tool for QDI Circuits Arithmetic Function Extractor (AFE) Decomposition Template Synthesizer (TSYN) Cell-Library Customization AES Implementation Conclusion References Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA Introduction Differential Power Analysis Dual Rail Logic: A Countermeasure Against DPA Secure Design Range Secure Triple Track Logic Conclusion References Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform Introduction Hybrid Reconfigurable Architecture Design Flow FPGA Mapping Procedure Experimental Results Set-Up Experimentation Conclusions References The Energy Scalability of Wavelet-Based, Scalable Video Decoding Introduction SystemOverview Energy Measurement Setup and First Results Energy Scalability Conclusions References Direct Memory Access Optimization in WirelessTerminals for Reduced Memory Latency and EnergyConsumption Introduction Related Work Overview of the Proposed Methodology Step 1: Dominant Scenario Definition Step 2: DMA Parameters Definition in Multi-threaded Systems Profiling Framework DMA Word Length and DMA Minimum Block Transfer Size Analysis of the Proposed HW/SW Modifications for the DMA Steps 3 and 4: Run-Time Scenario Identification and DMA Parameter Selection Experimental Results Conclusions References Exploiting Input Variations for Energy Reduction Introduction Typical-Case Design Methodologies Related Works Razor Logic Canary Logic Canary Flip-Flop Power Reduction with Canary FFs Canary FF Implementation Via Scan Reuse Evaluation Methodology Timing Error Rates Architectural-Level Simulation Environment Results Conclusions References A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates Introduction Different Differential Power Analyses Differential Power Analysis of Kocher Multi-bit DPA Design Oriented Modelling of DPA Syndrome Leaking Gates Identification εpVDD Distribution Analysis DPA Syndrome Analysis Critical and Uncritical Gates and Nets Conclusion References Static Power Consumption in CMOS Gates Using Independent Bodies Introduction Test Set-Up Simulation Results Input Patterns Containing the Controlling Value Input Patterns Not Containing the Controlling Value Conclusions References Moderate Inversion: Highlights for Low Voltage Design Introduction EKV 2.0 MOS Model Self Cascode Structure Traditional Approach Proposed Approach Temperature Considerations Measurements and Discussion Self Cascode Current Reference (SCCR) Current Reference Topology Design Equations Design Methodology Computer Simulation Results Conclusion References On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems Introduction Preliminaries Power-Aware Heuristic for Task Graphs Task Assignment and Online Voltage Scheduling Static Voltage Scheduling Experimental Results Conclusions References Semi Custom Design: A Case Study on SIMD Shufflers Introduction Motivation Design Methodology Choices Datapath Choice for Case Study SIMDShufflers Datapath Generator (DPG) Experimental Setup and Results Conclusions References Optimization for Real-Time Systems with Non-convex Power Versus Speed Models Introduction Power Model and Related Work Fundamental Problem Scheduling for Non-convex Power Model Experimental Results Conclusion References Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS Introduction Related Work Comparison of Standard Cell Libraries Static Power Calculations HSPICE Simulation Triple-Threshold Static Power Minimization Methodology Simulation Conclusion References A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits Introduction Related Work QDI Asynchronous Synthesis Method Persia Synthesis Tool High Level Power Estimation High-Level Simulation for Power Estimation Experimental Results Conclusions References Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates Introduction Related Works Subthreshold Leakage Model Subthreshold Leakage in Non-series-parallel Networks On-Transistors in Off-Networks Results Conclusions References A Platform for Mixed HW/SW AlgorithmSpecifications for the Exploration of SW and HW Partitioning Introduction State of the Art of Platforms Supporting Mixed HW/SW Implementations Description of the Virtual Socket Platform Details on HW Implementation and SW Support The Heart of Simplicity: HDL Modules Virtual Memory Accesses The Software Support: The Virtual Memory Window Library The Integration of the HDL Modules in the Platform Profiling Tools: Testing and Optimizing Data Transfers Conclusion References Fast Calculation of Permissible SlowdownFactors for Hard Real-Time Systems Introduction Related Work Model Event Streams Demand Bound Linear Programme Experiments Conclusion and Future Work References Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate Introduction Proposed Estimation Methodology Comparison Results Conclusions References A Statistical Model of Logic Gates for Monte CarloSimulation Including On-Chip Variations Introduction Statistical Gate Model Model Extraction Case Study Conclusions References Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data Introduction Correlated Input Data Proposed Approach Multiplier and Bus Power Consumption Selective Negation Results Design 1 Design 2 Design 3 Conclusion References Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply Introduction FGMOS Basics Full-Adder Designs Full-Adder Simulations Results Discussion Conclusions References Low-Power Digital Filtering Based on the Logarithmic Number System Introduction LNSBasics LNS Representation in the Implementation of Digital Filters Feedback Filters FIR Filters Power Dissipation of LNS Addition and Multiplication Discussion and Conclusions References A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling Introduction LDVS Architecture Proposal The Power Supply Selector PSS Architecture Hopping Sequence Results Power Efficiency PSS Area Transition Simulation Conclusion References Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers Introduction Fault Tolerance Integer Multipliers Fault-Tolerant Adders and Multipliers Time-Redundancy Techniques in Multipliers Technique 1 – Swapped Inputs Technique 2 – Inverted Reduction Tree Technique 3 – Inverted Reduction Tree and Swapped Inputs Technique 4 – Twin Precision Evaluation of the Time-Redundancy Techniques Fault Model Assessment 1 - 8×8-Bit Multiplier with CSA Reduction Tree Assessment 2 - 8×8-Bit Multiplier with HPM Reduction Tree Assessment 3 - 16×16-Bit Multiplier with CSA Reduction Tree Delay, Power, and Area Penalties Conclusion References Design and Industrialization Challenges of Memory Dominated SOCs Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies Analog Power Modelling Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters Author Index In 1999 a number of member states of the European Union will adopt a common currency. This change in the monetary system requires that a Eur­ opean Central Bank is set up and a common monetary policy is pursued. There is general agreement among those countries which are likely to join the common currency that price level stability has to be the ultimate objec­ tive of monetary po1icy. It is an open issue, however, what kind of policy is best suited for that purpose. The alternative strategies under discussion are a direct inflation targeting, an intermediate monetary targeting or a mixture of both. For these policy strategies a stable money demand relation is of cen­ tral importance. Therefore a workshop on Money Demand in Europe was organized at the Humboldt University in Berlin on October 10/11, 1997. This research conference brought together academic and central bank econo­ mists and econometricians predominantly from Europe to discuss issues on specification, estimation and, in particular, stability of money demand rela­ tions both in a single equation and in a systems framework. In this volume revised versions of the papers presented and discussed at the workshop are collected. The volume thereby gives an overview of money demand analysis in Europe on the eve of the introduction of the Euro in some European countries. It contributes to the discussion on a suitable monetary policy for the new European Central Bank. Annotation This book constitutes the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007. The 36 revised full papers and 19 revised poster papers presented together with the abstracts of 3 key notes and 2 industrial papers were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on high-level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, low power techniques and applications, as well as design challenges in real-life projects