Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems : IFIP TC 10 WG 10.5 International Conference on Computer Hardware Description Languages and Their Applications, 20-25

In the past few decades Computer Hardware Description Languages (CHDLs) have been a rapidly expanding subject area due to a number of factors, including the advancing complexity of digital electronics, the increasing prevalence of generic and programmable components of software-hardware and the migration of VLSI design to high level synthesis based on HDLs. Currently the subject has reached the consolidation phase in which languages and standards are being increasingly used, at the same time as the scope is being broadened to additional application areas. This book presents the latest developments in this area and provides a forum from which readers can learn from the past and look forward to what the future holds. Front Matter....Pages i-x Front Matter....Pages 1-1 Synchronous Languages for Hardware and Software Reactive Systems....Pages 3-3 Towards a Complete Design Method for Embedded Systems Using Predicate/Transition-Nets....Pages 4-23 Front Matter....Pages 25-25 Simplifying Data Operations for Formal Verification....Pages 27-39 CTL and Equivalent Sublanguages of CTL....Pages 40-59 Verifying linear temporal properties of data insensitive controllers using finite instantiations....Pages 60-73 A High-Level Language for Programming Complex Temporal Behaviors and Its Translation into Synchronous Circuits....Pages 74-76 System-Level Hardware Design with μ -Charts....Pages 77-79 Interface Synthesis in Embedded HW/SW Systems....Pages 80-82 TripleS — A Formal Validation Environment for Functional Specifications....Pages 83-85 SOFHIA: A CAD Environment to Design Digital Control Systems....Pages 86-88 Compiling the language Balsa to delay insensitive hardware....Pages 89-91 High-Level Synthesis of Structured Data Paths....Pages 92-94 Front Matter....Pages 95-95 Characterizing a portable subset of behavioral VHDL-93....Pages 97-113 Algebra of Communicating Timing Charts for Describing and Verifying Hardware Interfaces....Pages 114-133 A formal proof of absence of deadlock for any acyclic network of PCI buses....Pages 134-156 Front Matter....Pages 157-157 Behavioural Modelling of Sampled-Data Systems with HDL-A and ABSynth....Pages 159-177 Front Matter....Pages 179-179 Hardware Description Languages in Practical Design Flows....Pages 181-181 VHDL generation from SDL specifications....Pages 182-201 Exploiting Isomorphism for Speeding-Up Instance-Binding in an Integrated Scheduling, Allocation and Assignment Approach to Architectural Synthesis....Pages 202-211 Front Matter....Pages 213-213 Verification of Large Systems in Silicon....Pages 215-239 Front Matter....Pages 213-213 The Shall Design Test Development Model for Hardware Systems....Pages 240-259 Modular Operational Semantic Specification of Transport Triggered Architectures....Pages 260-279 Front Matter....Pages 281-281 The World of I/O: A Rich Application Area for Formal Methods....Pages 283-284 Abstract Modelling of Asynchronous Micropipeline Systems using Rainbow....Pages 285-304 A New Partial Order Reduction Algorithm for Concurrent System Verification....Pages 305-314 Front Matter....Pages 315-315 VHDL Power Simulator: Power Analysis at Gate-Level....Pages 317-333 Object Oriented Extensions to VHDL, The LaMI proposal....Pages 334-347 Back Matter....Pages 348-350