Formal methods for hardware verification : 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006 : advanced lectures

This book presents a set of 8 papers accompanying the lectures of leading researchers given at the 6th edition of the International School on Formal Methods for the Design of Computer, Communication and Software Systems, SFM 2006, held in Bertinoro, Italy in May 2006. SFM 2006 was devoted to formal techniques for hardware verification and covers several aspects of the hardware design process, including hardware design languages and simulation, property specification formalisms, automatic test pattern generation, symbolic trajectory evaluation, BDD-based and SAT-based model checking, decision procedures, refinement, theorem proving, and the verification of floating point units. Front Matter....Pages - Hardware Design and Simulation for Verification....Pages 1-29 Automatic Test Pattern Generation....Pages 30-55 An Introduction to Symbolic Trajectory Evaluation....Pages 56-77 BDD-Based Hardware Verification....Pages 78-107 SAT-Based Verification Methods and Applications in Hardware Verification....Pages 108-143 Building Efficient Decision Procedures on Top of SAT Solvers....Pages 144-175 Refinement and Theorem Proving....Pages 176-210 Floating-Point Verification Using Theorem Proving....Pages 211-242 Back Matter....Pages -

This book presents 8 papers accompanying the lectures of leading researchers given at the 6th edition of the International School on Formal Methods for the Design of Computer, Communication and Software Systems (SFM 2006). SFM 2006 was devoted to formal techniques for hardware verification and covers several aspects of the hardware design process, including hardware design languages and simulation, property specification formalisms, automatic test pattern generation, symbolic trajectory evaluation, and more.