Field-Programmable Logic: Architectures, Synthesis and Applications 4th International Workshop on Field-Programmable Logic and Applications, FPL'94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings

"This volume contains the proceedings of the 4th International Workshop on Field-Programmable Logic and Applications (FPL '94), held in Prague, Czech Republic in September 1994. The growing importance of field-programmable devices is substantiated by the remarkably high number of 116 submissions for FPL '94; from them, the revised versions of 40 full papers and 24 high-quality poster presentations were accepted for inclusion in this volume. Among the topics treated are: testing, layout, synthesis tools, compilation research and CAD, trade-offs and experience, innovations and smart applications, FPGA-based computer architectures, high-level design, prototyping and ASIC emulators, commercial devices, new tools, CCMs and HW/SW co-design, modelers, educational experience, and novel architectures."--PUBLISHER'S WEBSITE Fault modeling and test generation for FPGAs....Pages 1-10 A test methodology applied to Cellular logic Programmable Gate Arrays....Pages 11-22 Integrated layout synthesis for FPGA's....Pages 23-33 Influence of logic block layout architecture on FPGA performance....Pages 34-44 A global routing heuristic for FPGAs based on mean field annealing....Pages 45-56 Power dissipation driven FPGA place and route under delay constraints....Pages 57-65 FPGA technology mapping for power minimization....Pages 66-77 Specification and synthesis of complex arithmetic operators for FPGAs....Pages 78-88 A speed-up technique for synchronous circuits realized as LUT-based FPGAs....Pages 89-92 An efficient technique for mapping RTL structures onto FPGAs....Pages 99-110 A testbench design method suitable for FPGA-based prototyping of reactive systems....Pages 111-113 Using consensusless covers for fast operating on Boolean functions....Pages 114-116 Formal verification of timing rules in design specifications....Pages 117-119 Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures....Pages 120-122 A high-speed rotation processor....Pages 123-125 The MD5 message-digest algorithm in the XILINX FPGA....Pages 126-128 A reprogrammable processor for fractal image compression....Pages 129-131 Implementing GCD systolic Arrays on FPGA....Pages 132-134 Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems....Pages 135-137 Direct sequence spread spectrum digital Radio DSP prototyping using xilinx FPGAs....Pages 138-140 FPGA based reconfigurable architecture for a compact vision system....Pages 141-143 A new FPGA architecture for word-oriented datapaths....Pages 144-155 Image processing on a custom computing platform....Pages 156-167 A superscalar and reconfigurable processor....Pages 168-174 A fast FPGA implementation of a general purpose neuron....Pages 175-182 Data-procedural languages for FPL-based machines....Pages 183-191 Implementing on line arithmetic on PAM....Pages 196-207 Software environment for WASMII: A data driven machine with a virtual hardware....Pages 208-219 Constraint-based hierarchical placement of parallel programs....Pages 220-229 ZAREPTA: A zero lead-time, all reconfigurable system for emulation, prototyping and testing of ASICs....Pages 230-239 Simulating static and dynamic faults in BIST structures with a FPGA based emulator....Pages 240-250 FPGA based prototyping for verification and evaluation in hardware-software cosynthesis....Pages 251-258 FPGA based low cost Generic Reusable Module for the rapid prototyping of subsystems....Pages 259-270 FPGA development tools: Keeping pace with design complexity....Pages 271-273 Meaningful benchmarks for logic optimization of table-lookup FPGAs....Pages 274-276 Educational use of Field Programmable Gate Arrays....Pages 277-279 Hardwire: A risk-free FPGA-to-ASIC migration path....Pages 280-282 Reconfigurable hardware from programmable logic devices....Pages 283-285 On some limits of XILINX based control logic implementations....Pages 286-288 Experiences of using XBLOX for implementing a digital filter algorithm....Pages 289-291 Continuous interconnect provides solution to density/performance trade-off in programmable logic....Pages 292-294 A high density complex PLD family optimized for flexibility, predictability and 100% routability....Pages 295-297 Design experience with fine-grained FPGAs....Pages 298-302 FPGA routing structures from real circuits....Pages 303-305 A tool-set for simulating altera-PLDs using VHDL....Pages 306-308 A CAD tool for the development of an Extra-Fast Fuzzy Logic Controller based on FPGAs and memory modules....Pages 309-311 Performance characteristics of the Monte-Carlo clustering processor (MCCP) - a field programmable logic based custom computing machine....Pages 312-314 A Design Environment with Emulation of Prototypes for hardware/software systems using XILINX FPGA....Pages 315-317 DSP development with full-speed prototyping based on HW/SW codesign techniques....Pages 318-320 The architecture of a general-purpose processor cell....Pages 321-325 The design of a stack-based microprocessor....Pages 326-331 Implementation and performance evaluation of an image pre-processing chain on FPGA....Pages 332-334 Signature testability of PLA....Pages 335-337 A FPL prototyping package with a C++ interface for the PC bus....Pages 338-340 Design of safety systems using Field Programmable Gate Arrays....Pages 341-343 A job dispatcher-collector made of FPGA's for a centralized Voice Server....Pages 344-351 An optoelectronic 3-D Field Programmable Gate Array....Pages 352-360 On channel architecture and routability for FPGA's under faulty conditions....Pages 361-372 High-performance datapath implementation on Field-Programmable Multi-Chip Module (FPMCM)....Pages 373-383 A laboratory for a digital design course using FPGAs....Pages 385-396 Coordinate Rotation DIgital Computer (CORDIC) synthesis for FPGA....Pages 397-408 MARC: A Macintosh NUBUS-expansion board based reconfigurable test system for validating communication systems....Pages 409-420 Artificial neural network implementation on a fine-grained FPGA....Pages 421-431 As new technologies for the implementation of digital designs are developed there is also the need for adequate CAD tools to exploit new features or to address new problems. Reiner W. Hartenstein, Michal Z. Servít (eds.). Includes Bibliographical References And Index.