Fault diagnosis and fault tolerance a systematic approach to special topics ; with 23 tables

With the rapid growth of integration scale of VLSI chips and the present need for reliable computers in space exploration, fault diagnosis and fault toleran­ ce have become more important than before, and hence reveal a lot of interest­ ing topics which attract many researchers to make a great number of contribu­ tions to this field. In recent years, many new and significant results have been achieved. A quick scan over the proceedings of the conferences on fault­ tolerant computing and design automation as well as on testing will convince the reader of that. But unfortunately these achievements have not been entire­ ly reflected in the textbooks, so that there seems to be a gap for the new researcher who already has the basic knowledge and wants to begin research in this area. As a remedy for this deficiency, this book is intended for begin­ ners, especially graduate students, as a textbook which will lead them to the frontier of some branches of the fault-tolerant computing field. The first chapter introduces the four-valued logic B4 and its applica­ tions. In 1966 Roth first proposed this four-valued logic as a technique to generate tests for logical circuits, but this work did not concern the mathe­ matical basis of B4 itself. With the rapid growth of scale of integration of VLSI chips and the need forreliable computers, fault diagnosis and fault tolerance have become important topics in chip design and manufacture. This book is intended to lead new researchers in the field to the frontier of some branches of the fault-tolerant computing field. The book presents the results of a research group working at Chongqing University, China, for the last twelveyears. It contains seven chapters that can be read independently of each other. Chapter 1 gives a mathematical introduction to four-valued logic and its applications to test generation, hazard identification, and transition logic. Chapter 2 summarizes work on the fault-diagnosis problem at the system level, with society diagnosis and an analog circuit as examples. Chapter 3 discusses the definition of a testability measure, introduces the synthesis problem for testability, and studies automatic design for testability at gate level and module level. Chapter 4 introduces the new NMRC (N-modular redundancy with comparing) technique and studies some optimal designs. Chapter 5 studies the fault-tolerance of interconnection switching networks and shows how networks can be designed to increase the tolerated number of faulty elements. Chapter 6 shows how fault-tolerance problems for multibus systems correspond to connectivity problems for hypergraphs and how optimal connectivity is achieved with BIB (balanced incomplete block) designs. Chapter 7 discusses TMR (triple modular redundancy) systems Front Matter....Pages I-XII Four-Valued Logic and Its Applications....Pages 1-64 Computer System Diagnosis and Society Diagnosis....Pages 65-94 Testability Design via Testability Measures....Pages 95-118 NMRC: A Technique for Redundancy....Pages 119-134 Fault Tolerance of Switching Interconnection ß-Networks....Pages 135-156 The Connectivity of Hypergraph and the Design of Fault Tolerant Multibus Systems....Pages 157-183 TMR Design of Distributed System for Sequential Faults....Pages 185-197