معرفی کتاب «Electronic Devices Architectures for the NANO-CMOS Era : From Ultimate CMOS Scaling to Beyond CMOS Devices» نوشتهٔ Simon Deleonibus, Simon Deleonibus، منتشرشده توسط نشر Pan Stanford; Distributed by World Scientific; Jenny Stanford Publishing در سال 2008. این کتاب در 439 صفحه، فرمت pdf، زبان انگلیسی ارائه شده است.
This book gives a state-of-the-art overview by internationally-recognized researchers of the electronic device architectures required for the NanoCMOS era and beyond. Challenges relevant to the scaling of CMOS Nanoelectronics are addressed through the different Core CMOS and Memory Devices options in the first part of the book. The second part reviews the New device Concepts for Nanoelectronics Beyond CMOS. What are the fundamental limits of core CMOS, and can we improve the scaling by the introduction of new materials or processes? Will the new architectures using SOI, multigates, or multichannels improve the trade-off between performance and power consumption and relax the constraints of new material integration? Can quantum computing replace binary-based protocols to enhance the information processing power? These questions and others are answered in this book. Contents: CMOS Nanoelectronics. Reaching the End of the Roadmap: Core CMOS: Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond (S Deleonibus, O Faynot, B de Salvo, T Ernst, C Le Royer, T Poiroux & M Vinet); Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization (T Poiroux & G Le Carval); Devices Structures and Carrier Transport Properties of Advanced CMOS using High Mobility Channels (S Takagi, T Tezuka, T Irisawa, S Nakaharai, T Numata, K Usuda, N Sugiyama, M Shichijo, R Nakane & S Sugahara); High-kappa Gate Dielectrics (H Wong, K Shiraishi, K Kakushima & H Iwai); Fabrication of Source and Drain Ultra Shallow Junction (B Mizuno); New Interconnect Schemes: End of Copper, Optical Interconnects? (S Laval, L Vivien, E Cassan, D Marris-Morini & J-M Fédéli); Memory Devices: Technologies and Key Design Issues for Memory Devices (K Kim & G Jeong); FeRAM and MRAM Technologies (Y Arimoto); Advanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices (B De Salvo & G Molas); New Concepts for Nanoelectronics. New Paths Added to CMOS Beyond the End of the Roadmap: Single Electron Devices and Applications (J Gautier, X Jehl & M Sanquer); Electronic Properties of Organic Monolayers and Molecular Devices (D Vuillaume); Carbon Nanotube Electronics (V Derycke, A Filoramo & J-P Bourgoin); Spin Electronics (K-J Lee & S H Lim); The Longer Term: Quantum Information Processing and Communication (P Jorrand).
in-depth And Timely, This Examination Gives A State-of-the-art Overview By Internationally-recognized Researchers Of The Electronic Device Architectures Required For The Nanocmos Era And Beyond. Challenges Relevant To The Scaling Of Cmos Nanoelectronics Are Addressed Through The Different Core Cmos And Memory Devices Options In The First Part Of The Book. The Second Part Reviews The New Device Concepts For Nanoelectronics Beyond Cmos. What Are The Fundamental Limits Of Core Cmos, And Can We Improve The Scaling By The Introduction Of New Materials Or Processes? Will The New Architectures Using Soi, Multigates, Or Multichannels Improve The Trade-off Between Performance And Power Consumption And Relax The Constraints Of New Material Integration? Can Quantum Computing Replace Binary-based Protocols To Enhance The Information Processing Power? These Questions And Others Are Answered In This Book.
In this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. Challenges relevant to the scaling of CMOS nanoelectronics are addressed through different core CMOS and memory device options in the first part of the book. The second part reviews new device concepts for nanoelectronics beyond CMOS. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes, new architectures using SOI, multigates and multichannels, and quantum computing. What are the fundamental limits of core CMOS, and can we improve the scaling by the introduction of new materials or processes? Can quantum computing replace binary-based protocols to enhance the information processing power? This title answers these questions and others