Designing Modern Embedded Systems: Software, Hardware, and Applications : 7th IFIP TC 10 International Embedded Systems Symposium, IESS 2022, Lippstadt, Germany, November 3–4, 2022, Proceedings

This book constitutes the refereed proceedings of the 7th IFIP TC 10 International Embedded Systems Symposium, IESS 2022, held in Lippstadt, Germany, during November 3-4, 2022. The 10 full revised papers and 2 short papers presented were carefully reviewed and selected from 13 submissions. The presented research and technical works cover system-level design methods, algorithms, verification and validation techniques, estimation of system properties and characteristics, performance analysis, and real-time systems design. Also, the book presents industrial and real-world application case studies that discuss the challenges and realizations of modern embedded systems, especially when it comes to including artificial intelligence algorithms and techniques in embedded systems. Preface IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS) November 3–4, 2022 Lippstadt, Germany Contents Design Methods and Model-Driven Engineering Evaluating the Perceptual Properties of Crosscutting Concerns Occurrence Points Specifications in Embedded Software 1 Introduction 2 Overview of the Physics of Notations Framework 3 Related Work 4 Evaluation Framework 5 Empirical Experiments and Results 6 Limitations and Threats to Validity 7 Conclusions and Future Work References Simulation of Timing Attacks and Challenges for Early Side-Channel Security Analysis 1 Introduction 2 Overview: Side-Channel and Timing Attacks 3 Related Work 4 Modeling and Simulation of Kocher's Timing Attack 4.1 General Test Setup and Procedure 4.2 Modeling Time 4.3 Results and Improvements 4.4 Discussion 5 Conclusion References Adaptation for Energy Saving in Time-Triggered Systems Using Meta-scheduling with Sample Points 1 Introduction 2 Related Work 3 Proposed Approach 3.1 Adaptation in Time-Triggered Multi-core Architectures 3.2 Context Agreement 3.3 Meta-scheduling with Sample Points for Adaptation 4 Experimental Setup 4.1 Time-Triggered Multi-core Architecture 4.2 Meta-scheduler with Sample Points 5 Results and Discussion 6 Conclusion References Communication Layer Architecture for a Production Line Digital Twin Using Hierarchical Colored Petri Nets 1 Introduction 2 Related Works 2.1 Place as a Physical Input 2.2 Petri Net as a Messenger Between AI and the World 3 Concept of Communication Layer Architecture for a Digital Twin Using Hierarchical Colored Petri Nets 3.1 Digital Twin 3.2 Layer Architecture 4 Use Case Implementation: Vertical Farming 4.1 Real Line 4.2 Digital Twin Pair 5 Conclusion References Hardware Architectures for Embedded Systems Exploiting Heterogeneity in PIM Architectures for Data-Intensive Applications 1 Introduction 2 Background and Related Work 3 PIM Opportunities for Heterogeneous Data-Intensive Processing 4 Near-data Architecture for Heterogeneous Execution 5 Experimental Setup and Results 5.1 Evaluation Setup 5.2 Results 6 Conclusion and Future Work References Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0*-4pt 1 Introduction 1.1 Background and Related Work 1.2 Problem Definition 2 The ``Checkerboard'' Grid of Processing Cells 2.1 Overview of Checkerboard SystemC Model 3 Mandelbrot Set Visualization on Checkerboard 3.1 Theoretical Model of Mandelbrot Set Visualization 3.2 Mapping on the Checkerboard Model 4 Experiments and Results 4.1 Experimental Setup 4.2 Results and Evaluation for the Theoretical Model 4.3 Results and Evaluation for the Checkerboard Model 4.4 Comparison 5 Conclusion References MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference 1 Introduction 2 Motivational Example 3 Related Work 4 Memory-Aware Fusing and Tiling (MAFAT) 4.1 Predicting Maximum Memory Usage 4.2 Configuration Algorithm 5 Experimental Results 5.1 Manual Exploration 5.2 Algorithm Performance 6 Summary and Conclusions References Memristor-only LSTM Acceleration with Non-linear Activation Functions 1 Introduction 2 Background 2.1 ReRAM for In-memory NN Computing 2.2 LSTM Architecture 3 Related Work 4 Proposed Architecture 4.1 MVM Unit 4.2 Programmable Non-Linear Unit (PNLU) 4.3 Hadamard Product Unit (HPU) 4.4 Local Buffers 4.5 Controller 5 Experimental Setup and Results 5.1 Methodology 5.2 Power and Area Analysis 5.3 Inference Accuracy 5.4 Computing Efficiency 6 Conclusion and Future Work References Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells 1 Introduction 1.1 Problem Definition 1.2 Background and Related Work 2 Modeling of the Checkerboard GPC 2.1 Modeling Interconnect Contention 3 Parallelized APNG Encoder Application 3.1 Backannotation of Delays 4 Mapping APNG on the Checkerboard 4.1 Checkerboard Mappings 5 Experimental Results 5.1 Models for Comparison 5.2 Measurement of Delays 5.3 Simulated Time Results 5.4 Observations and Comparison 6 Conclusion References Engineering Applications of Artificial Intelligence Targeting Embedded Systems Analysing the Characteristics of Neural Networks for the Recognition of Sugar Beets 1 Introduction 2 Related Work 3 Analysing the Models 4 Analysis of the Characteristics 5 Summary and Outlook References Synthetic Data for Machine Learning on Embedded Systems in Precision Agriculture 1 Motivation 2 Related Work 3 Solution 3.1 Datasets 3.2 Process Overview 3.3 Synthetic Dataset 4 Evaluation 5 Summary and Outlook References Using Network Architecture Search for Optimizing Tensor Compression 1 Introduction 2 Related Works 2.1 Tensor Compression 2.2 Tucker Decomposition 2.3 Model Optimization Using NAS 3 Tensor Compression Implementation 4 NAS Setup 4.1 Evaluation Metric 5 Evaluation 6 Conclusion References Author Index