روش‌شناسی طراحی برای حلقه‌های قفل‌فاز RF CMOS

Engineers face stiff challenges in designing phase-locked loop (PLL) circuits for wireless communications thanks to phase noise and other obstacles. This practical book comes to the rescue with a proven PLL design and optimization methodology that lets designers assess their options, predict PLL behavior, and develop cost-effective PLLs that meet performance requirements no matter what IC (integrated circuit) challenges they come up against. This uniquely comprehensive toolkit takes designers step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. It provides a sample design of a fully integrated PLL for WLAN applications, demonstrating every step from specs definition and circuit characterization to layout generation and circuit schematics. Design Methodology for RF CMOS Phase Locked Loops......Page 2 Contents......Page 6 Preface......Page 12 1 Approach to CMOS PLL Design......Page 14 1.1.1 Enhancement Type MOSFET Structure......Page 15 1.1.2 Operating Principles of the N-Channel MOSFET Transistor......Page 17 1.2.1 Channel-Length Modulation......Page 20 1.2.2 Parasitic Capacitances......Page 22 1.2.3 Gate Resistance......Page 23 1.2.4 Body Effect......Page 24 1.3 Impact on PLL Performance......Page 25 1.3.1 Phase Noise......Page 26 1.3.2 Parasitic Capacitances and PLL Behavior......Page 27 1.4 State of the Art and Challenges in CMOS PLL Design......Page 28 1.5 PLL Design Flow......Page 30 1.6 Basic Design Bibliography......Page 31 References......Page 33 2.1 Frequency Synthesizer......Page 36 2.1.1 Integer-N Architecture......Page 38 2.1.2 Fractional Architecture......Page 40 2.2.1 Phase Noise......Page 42 2.2.2 Spurious Emissions......Page 47 2.2.3 Lock Time......Page 51 References......Page 53 3.1 Functional Description......Page 56 3.2 Types of LC-Tank Oscillators......Page 58 3.2.1 NMOS......Page 59 3.2.2 PMOS......Page 60 3.2.3 CMOS......Page 61 3.3.1 Integrated Inductors......Page 62 3.3.2 Integrated Varactors......Page 65 3.4 LC-Tank Oscillator Phase Noise......Page 71 3.4.1 Definition of Phase Noise......Page 72 3.4.2 The Leeson Model......Page 75 3.5 Designing the Layout of the Oscillator......Page 80 References......Page 83 4.1 Basic Frequency Dividers......Page 88 4.2 High-Frequency Divider Architectures and Building Blocks......Page 90 4.3 High-Frequency Divider-by-2......Page 92 4.3.1 Razavi......Page 94 4.3.2 Wang......Page 95 4.3.3 SCL......Page 96 4.4 Dual-Modulus Prescaler......Page 97 4.5 Low-Frequency Dividers......Page 99 4.6 Phase Noise......Page 101 4.7 Layout Considerations......Page 104 References......Page 105 5 Phase Frequency Detector/Phase Detector......Page 106 5.2 Exclusive-OR Logic Gate......Page 107 5.4 PFD/CP......Page 108 5.5.1 The Craninckx Model......Page 114 5.5.2 The Banerjee Model......Page 115 5.6.1 Design of the PFD......Page 116 5.6.2 Design of the Charge Pump......Page 117 5.7 Design of the Layout of the Phase Detector......Page 119 References......Page 120 6 Determination of Building Blocks Specifications......Page 122 6.1 Initial Requirements......Page 123 6.1.2 Reference Crystal......Page 124 6.1.3 Phase Noise......Page 125 6.1.5 Lock Time......Page 128 6.2 Architecture Selection......Page 129 6.3 Ad Hoc Simulation Tool: Simusyn......Page 130 6.3.1 Simusyn Description......Page 131 6.3.2 Models Implemented in Simusyn......Page 132 6.4.2 VCO......Page 134 6.4.3 Phase Detector......Page 137 6.4.5 Global Specifications of the Loop......Page 139 References......Page 141 7.1 Choice of Architecture of the Oscillator......Page 144 7.1.2 Active Circuit......Page 145 7.1.3 Output Stage......Page 146 7.2.1 Basic Expressions for the Design of the VCO......Page 147 7.2.2 Design and Selection of the Tank Circuit......Page 149 7.2.3 Design of the Schematic Circuit of the Oscillator......Page 156 7.2.4 Layout Implementation......Page 161 References......Page 163 8.1 Choice of the Architecture of the Divider......Page 164 8.1.2 Differential to Single-Ended Converter......Page 165 8.1.3 Low-Frequency Digital Divider......Page 166 8.2 Design of the Frequency Divider......Page 168 8.2.1 High-Frequency Divider-by-2 and Converter......Page 169 8.2.2 Low-Frequency Divider......Page 171 8.3 Design of the Schematic Circuit of the Divider......Page 173 8.3.2 Introduction of Auxiliary Components......Page 175 8.4 Divisor Layout Generation and Simulation......Page 178 References......Page 183 9.1 Choice of the Architecture of the Detector......Page 184 9.2.1 Design of the PFD......Page 188 9.2.2 Design of the Charge Pump......Page 191 9.2.3 Design of the Schematic Circuit of the Phase Frequency Detector......Page 194 9.2.4 Postlayout Simulations of the Phase Detector......Page 198 References......Page 201 10.1 General Considerations......Page 202 10.2 Schematic Circuit Design of the Synthesizer......Page 203 10.3 Layout of the Synthesizer......Page 208 11.1 VCO......Page 214 11.2 Frequency Divider......Page 218 11.3 Complete PLL......Page 221 11.4 Result Discussion......Page 226 References......Page 228 About the Authors......Page 230 Index......Page 232

Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against.
After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.

Engineers face stiff challenges in designing phase-locked loop (PLL) circuits for wireless communications thanks to phase noise and other obstacles. This book features a PLL design and optimization methodology that lets designers assess their options, predict PLL behavior, and develop cost-effective PLLs that meet performance requirements.