Design Automation of Real-Life Asynchronous Devices and Systems (Foundations and Trends(R) in Electronic Design Automation)

The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. However, the electronics industry for the most part is still reluctant to adopt asynchronous design due to a common belief that there is a lack of commercial-quality Electronic Design Automation tools for asynchronous circuits. Design Automation of Real-Life Asynchronous Devices and Systems presents design flows that can tackle large designs without significant changes with respect to synchronous design flow. Limiting it self to the four design flows that come closest to this goal it starts by overviewing the most commercially and technically proven, Tangram. The other three flows, Null Convention Logic, de-synchronization and gate-level pipelining, can be considered as asynchronous re-implementations of synchronous specifications. Design Automation of Real-Life Asynchronous Devices and Systems demonstrates the possibility of implementing large legacy synchronous designs in an almost "push button" manner negating the need to re-educate synchronous RTL designers. It is essential reading for designers and researchers in large scale integrated circuit design. The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines Requirements for an Asynchronous Design Flow......Page 14 Motivation for Asynchronous Approach......Page 17 Asynchronous Design......Page 20 An Overview of Asynchronous Design Styles......Page 22 Asynchronous Design Flows......Page 24 Paper Organization......Page 29 Motivation......Page 32 Design Language Haste......Page 34 Handshake Circuits......Page 42 Handshake Implementations......Page 45 Library Connection......Page 47 Simulation and Verification......Page 48 Structural Design Flow......Page 49 Physical Design......Page 52 Overview......Page 56 Null Convention Logic......Page 58 NCL Design Flow with HDL Tools......Page 62 DIMS-based NCL Design Flow......Page 64 NCL Flow with Explicit Completeness......Page 66 Verification of NCL Circuits......Page 68 Introduction......Page 76 Signal Transition Graphs......Page 77 Revisiting Synchronous Circuits......Page 79 Relaxing the Synchronous Requirement......Page 81 Minimum Requirements for Correct Asynchronous Communication......Page 82 Handshake Protocols for De-synchronization......Page 89 Implementation of Handshake Controllers......Page 93 Design Flow......Page 95 Why De-synchronize?......Page 96 Conclusions......Page 97 Automated Pipelining: Motivation......Page 98 Automated Gate-Level Pipelining: General Approach......Page 101 Micropipeline Stages: QDI Template......Page 104 Design Flow Basics......Page 105 Fine-Grain Pipelining with Registers......Page 106 Pipeline Petri Net Model of the Flow......Page 108 Weaving: Simple Examples......Page 113 Low-Power Robust Design Using Haste......Page 120 Low-Power Robust Design using De-synchronization......Page 122 Design of Cryptographic Coprocessor......Page 124 Conclusions......Page 134 Acknowledgments......Page 138 References......Page 140 Presents design flows that can tackle large designs without significant changes with respect to synchronous design flow. The book demonstrates the possibility of implementing large legacy synchronous designs in an almost "push button" manner negating the need to re-educate synchronous RTL designers.