Design and Architecture for Signal and Image Processing: 16th International Workshop, DASIP 2023, Toulouse, France, January 16–18, 2023, Proceedings (Lecture Notes in Computer Science)

This book constitutes the thoroughly refereed conference proceedings of the 16th International Workshop on Design and Architecture for Signal and Image Processing, DASIP 2023, held in Toulouse, France in January 2023. The 9 full included in the volume were carefully reviewed and selected from 17 submissions. They are organized in the following topical sections: Methods and Applications, Hardware Architectures and Implementations and others. Preface Organization Contents Methods and Applications SCAPE: HW-Aware Clustering of Dataflow Actors for Tunable Scheduling Complexity 1 Introduction 2 Context and Related Work 2.1 SDF Based Dataow MoCs 2.2 Classic Flattening Method 2.3 Cluster of SDF Actors 3 SCAPE Method 3.1 Design Space Exploration Optimisation 3.2 Code Generation 4 Experiments 4.1 Experimental Setup 4.2 Analysis Time Evaluation 4.3 Latency Evaluation 5 Conclusion References Deep Recurrent Neural Network Performing Spectral Recurrence on Hyperspectral Images for Brain Tissue Classification 1 Introduction 2 Background 2.1 Hyperspectral Imaging 2.2 Machine Learning Algorithms 2.3 Hyperparameter Optimization 3 Methodology 3.1 Input Data 3.2 Deep Recurrent Neural Network Architecture 3.3 Training Process 4 Experiments and Results 4.1 Test Bench 4.2 Metrics Evaluated 4.3 Analysis 5 Conclusions and Future Work References Brain Blood Vessel Segmentation in Hyperspectral Images Through Linear Operators 1 Introduction 2 Background 3 Algorithm and Implementation 3.1 Optimization 3.2 Acceleration 4 Experiments and Results 4.1 Objective Results 4.2 Subjective Results 5 Conclusions and Future Work References Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes 1 Introduction 2 Related Work 3 Proposed Solution 3.1 RNN Model 3.2 Model Implementation 4 Experimental Evaluation 4.1 Considered Datasets 4.2 Network Parameterization 4.3 Accuracy Results 4.4 Execution Performance and Required Resources 4.5 Comparison with Other Approaches 5 Conclusions References Hardware Architectures and Implementations AINoC: New Interconnect for Future Deep Neural Network Accelerators 1 Introduction 2 Related Work 3 AINoC architecture 3.1 Parallel Routing Device 3.2 AINoC Features 3.3 Dataflow Model 4 Experiment Results 4.1 Evaluation Methodology 4.2 FPGA Implementation Results 5 Conclusion References Real-Time FPGA Implementation of the Semi-global Matching Stereo Vision Algorithm for a 4K/UHD Video Stream 1 Introduction 2 The SGM Algorithm 3 Previous Work 4 The Proposed Hardware Implementation 4.1 Determination of the Matching Cost 4.2 Cost Aggregation 4.3 Evaluation of the Proposed Method 4.4 Hardware Implementation 5 Conclusion References TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing 1 Introduction 2 Fundamentals 3 Related Work 4 Hardware/Software Co-designed Fuzzer 4.1 Hardware - Interconnects (PE Ports) 4.2 Hardware - Processor Core 4.3 Hardware - Fuzzer Result Aggregation 4.4 Hardware Modifications for More Effective Fuzzing 4.5 Fuzzer Software Architecture 5 Evaluation 5.1 FPGA Design Resources 5.2 Fuzzing Performance 5.3 Hash Collisions 6 Conclusion and Future Work References Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification 1 Introduction 2 Background and Related Work 2.1 Deep Learning for Radio Signal Classification 2.2 FPGAs and Deep Neural Network Accelerators 3 System Overview 3.1 Design-Time 3.2 Runtime 4 Methodology 5 Results 5.1 AIR-5G at Design-time 5.2 AIR-5G at Runtime 6 Conclusion References High-Level Online Power Monitoring of FPGA IP Based on Machine Learning 1 Introduction 2 Related Work 3 Methodology 3.1 IP Characterization System 3.2 Proposed Model 3.3 Hardware Implementation 4 Experimental Results 4.1 Test Cases 4.2 Model Assessment 5 Conclusion References Author Index