Correct hardware design and verification methods: IFIP WG10.2 Advanced Research Working Conference, CHARME '93, Arles, Frances [sic], May 24-26, 1993: proceedings

"These proceedings contain the papers presented at the Advanced Research Working Conference on Correct Hardware Design Methodologies, held in Arles, France, in May 1993, and organized by the ESPRIT Working Group 6018 CHARME-2and the Universit de Provence, Marseille, in cooperation with IFIP Working Group 10.2. Formal verification is emerging as a plausible alternative to exhaustive simulation for establishing correct digital hardware designs. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems, slowing the arrival of products in the marketplace with its associated increase in cost. From being a predominantly academic area of study until a few years ago, formal design and verification techniques are now beginning to migrate into industrial use. As we are now witnessing an increase in activity in this area in both academia and industry, the aim of this working conference was to bring together researchers and users from both communities."--PUBLISHER'S WEBSITE A graph-based method for timing diagrams representation and verification....Pages 1-14 A Petri Net approach for the analysis of VHDL descriptions....Pages 15-26 Temporal analysis of time bounded digital systems....Pages 27-38 Strongly-typed theory of structures and behaviours....Pages 39-54 Verification and diagnosis of digital systems by ternary reasoning....Pages 55-67 Logic verification of incomplete functions and design error location....Pages 68-79 A methodology for system-level design for verifiability....Pages 80-91 Algebraic models and the correctness of microprocessors....Pages 92-108 Combining symbolic evaluation and object oriented approach for verifying processor-like architectures at the RT-level....Pages 109-121 A theory of generic interpreters....Pages 122-134 Towards verifying large(r) systems: A strategy and an experiment....Pages 135-154 Advancements in symbolic traversal techniques....Pages 155-166 Automatic verification of speed-independent circuit designs using the Circal system....Pages 167-178 Correct compilation of specifications to deterministic asynchronous circuits....Pages 179-190 DDD-FM9001: Derivation of a verified microprocessor....Pages 191-202 Calculational derivation of a counter with bounded response time....Pages 203-213 Towards a provably correct hardware implementation of occam....Pages 214-225 Rewriting with constraints in T-ruby....Pages 226-241 Embedding hardware verification within a commercial design framework....Pages 242-257 An approach to formalization of data flow graphs....Pages 258-269

These proceedings contain the papers presented at the Advanced Research Working Conference on Correct Hardware Design Methodologies, held in Arles, France, in May 1993,
and organized by the ESPRIT Working Group 6018 CHARME-2and the Universit de Provence, Marseille, in cooperation with IFIP Working Group 10.2.
Formal verification is emerging as a plausible alternative to exhaustive simulation for establishing correct digital hardware designs. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems, slowing the arrival of products in the marketplace with its associated increase in cost. From being a predominantly academic area of study until a few years ago,
formal design and verification techniques are now beginning to migrate into industrial use. As we are now witnessing an increase in activity in this area in both academia and industry, the aim of this working conference was to bring together researchers and users from both communities.

Annotation These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2. Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago, formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities