Computing Platforms for Software-Defined Radio

This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability. Front Matter....Pages i-xii The Evolution of Software-Defined Radio: An Introduction....Pages 1-4 Front Matter....Pages 5-5 Design Transformation from a Single-Core to a Multi-Core Architecture Targeting Massively Parallel Signal Processing Algorithms....Pages 7-28 The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio....Pages 29-59 Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array....Pages 61-89 Reconfigurable Multiprocessor Systems-on-Chip....Pages 91-105 Ninesilica: A Homogeneous MPSoC Approach for SDR Platforms....Pages 107-119 Front Matter....Pages 121-121 Application of the Scalable Communications Core as an SDR Baseband....Pages 123-145 HW/SW Co-design Toolset for Customization of Exposed Datapath Processors....Pages 147-164 FPGA-Based Cognitive Radio Platform with Reconfigurable Front-End and Antenna....Pages 165-187 Synchronization in NC-OFDM-Based Cognitive Radio Platforms....Pages 189-207 Towards Adaptive Cryptography and Security with Software Defined Platforms....Pages 209-236 The Future of Software-Defined Radio: Recommendations....Pages 237-238 Back Matter....Pages 239-240 This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. Coverage includes architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability. Describes a computer engineering approach to SDR baseband processing hardware; Discusses implementation of numerous compute-intensive signal processing algorithms on single and multicore platforms; Enables deep understanding of optimization techniques related to power and energy consumption of multicore platforms using several basic and high-level performance indicators; Includes prototyping details of single and multicore platforms on ASICs and FPGAs