Computer Hardware Description Languages and Their Applications : Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and Their Applications - CHDL '93 Sponsored by IFIP WG10.2 and in Cooperation with IEE

Hardware description languages (HDLs) have established themselves as one of the principal means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods and many other related advances. This research-oriented publication aims to make a strong contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification Content: IFIP Transactions A: Computer Science and Technology, Page ii Front Matter, Page iii Copyright, Page iv Preface, Pages v-vi, David Agnew, Luc Claesen, Raul Camposano Conference organization, Pages vii-ix Real-time Distributed Systems, Pages 3-12, Mario R. Barbacci Verification of the Futurebus+ Cache Coherence Protocol, Pages 15-30, Edmund M. Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David E. Long, Kenneth L. McMillan, Linda A. Ness Exploiting symbolic traversal techniques for efficient Process Algebra Manipulation, Pages 31-44, Paolo Camurati, Fulvio Corno, Paolo Prinetto Hardware-Verification using First Order BDDs, Pages 45-62, Klaus Schneider, Ramayya Kumar, Thomas Kropf HW/SW Co-Design With PRAMs Using CODES, Pages 65-78, K. Buchenrieder, A. Sedlmeier, C. Veith Prevail-DM: a framework-based environment for formal hardware verification, Pages 79-96, Flávio R. Wagner Better Verification Through Symmetry, Pages 97-111, C. Norris Ip, David L. Dill A rewriting based method for the formal verification of microprocessors, Pages 115-122, M. Allemand REASONING ABOUT THE VHDL STANDARD LOGIC PACKAGE SIGNAL DATA TYPE, Pages 123-130, J.W. Gambles, P.J. Windley An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area, Pages 131-138, Xing-Jian Xu, Mitsuru Ishizuka Integrating Boolean Verification with Formal Derivation, Pages 139-146, Bhaskar Bose, Steven D. Johnson, Shyamsundar Pullela Automated high-level verification against clocked algorithmic specifications, Pages 147-154, Francisco Corella The Backward Walk Approach in FSM Verification, Pages 155-162, Stefan Krischer Automatic Verification of Sequential Circuit Designs, Page 165, Edmund M. Clarke Toward a Basis for Protocol Specification and Process Decomposition, Pages 169-186, Kamlesh Rath, Steven D. Johnson Integrating SDL and VHDL for System-Level Hardware Design, Pages 187-204, Wolfgang Glunz, Thomas Kruse, Torsten Rössel, Dieter Monjau Reasoning About Array Structures Using a Dependently Typed Logic, Pages 207-224, Alan Dent, Keith Hanna VHDL Description and Formal Verification of Systolic Multipliers, Pages 225-242, Laurence PIERRE Transformational Rewriting with Ruby, Pages 243-260, Robin Sharp, Ole Rasmussen A Representation for the Binding of RT-Component Functionality to HDL Behavior, Pages 263-280, Roger P. Ang, Nikil D. Dutt Performance Specification and Measurement, Pages 281-298, Ram Mandayam, Ranga Vemuri Automatic Synthesis of Sequential Synchronizations, Pages 299-315, Zheng Zhu, Steven D. Johnson SPECIFYING HARDWARE SYSTEMS IN LOTOS, Pages 319-326, Mohammed Faci, Luigi Logrippo HML: A Hardware Description Language Based on Standard ML, Pages 327-334, John O'Leary, Mark Linderman, Miriam Leeser, Mark Aagaard An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems, Pages 335-344, Bran Selic Linking system design tools and hardware design tools, Pages 345-351, A.A. Jerraya, K. O'Brien, T. Ben Ismail Automatic VHDL Model Generation System, Pages 353-360, Sungho Kang, Stephen A. Szygenda The Modeler's Assistant: A CAD Tool For Behavioral Model Development, Pages 361-368, Balraj Singh, John Wicks, Philip Wright, James R. Armstrong Insulin: An Instruction Set Simulation Environment, Pages 369-376, Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar Specification languages for communication protocols, Pages 379-396, Gregor v. Bochmann Integrating Behavior and Timing in Executable Specifications, Pages 399-416, K. Khordoc, M. Dufresne, E. Cerny, P.A. Babkine, A. Silburt ESP: An Executable Specification Language for Mixed Timing Control Circuits, Pages 417-434, Tam-Anh Chu, Huy T. Cao, Clement K.C. Leung UDL/I Version Two: A New Horizon of HDL Standards, Pages 437-452, Tamio Hoshino Verilog HDL Modeling Styles for Formal Verification, Pages 453-465, Felice Balarin, Gary York A Visual Hardware Description Language, Pages 467-484, Eric J. Golin, Annette C. Feng Textual/Graphical Design Capture for Concept-Level Synthesis, Pages 485-502, Walling R. Cyre System-Level Specification and Design Using VHDL A Case Study, Pages 505-522, Wolfgang Ecker, Sabine März A Denotational Definition of the VHDL Simulation Kernel, Pages 523-535, Karen C. Davis Checking DFT Rules with a VHDL Simulator, Pages 537-550, Wolfgang Glunz, Torsten Rössel Parametrized VHDL entities for the simulation of hybrid circuits, Pages 551-567, Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models, Pages 569-586, Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Vai Analog-VHDL : As an application, a real example, Pages 587-604, Dominique RODRIGUEZ IFIP, Pages 605-609 This research-oriented publication makes a contribution to further developments in the field of hardware description languages (HDLs). The text includes coverage of: BDD-based systems design and analysis; system level formal verification; and languages for protocol specification.