Compiler Construction : 12th International Conference, CC 2003, Held As Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003, Proceedings

This book constitutes the refereed proceedings of the 12th International Conference on Compiler Construction, CC 2003, held in Warsaw, Poland, in April 2003. The 20 revised full regular papers and one tool demonstration paper presented together with two invited papers were carefully reviewed and selected from 83 submissions. The papers are organized in topical sections on register allocation, language constructs and their implementation, type analysis, Java, pot pourri, and optimization. Combined Code Motion and Register Allocation Using the Value State Dependence Graph....Pages 1-16 Early Control of Register Pressure for Software Pipelined Loops....Pages 17-32 Register Allocation by Optimal Graph Coloring....Pages 33-45 A Compilation and Optimization Model for Aspect-Oriented Programs....Pages 46-60 A Pattern Matching Compiler for Multiple Target Languages....Pages 61-76 A New One-Pass Transformation into Monadic Normal Form....Pages 77-89 Run-Time Type Checking for Binary Programs....Pages 90-105 Precision in Practice: A Type-Preserving Java Compiler....Pages 106-120 The MAGICA Type Inference Engine for MATLAB ®....Pages 121-125 Dimensions of Precision in Reference Analysis of Object-Oriented Programming Languages....Pages 126-137 Polyglot: An Extensible Compiler Framework for Java....Pages 138-152 Scaling Java Points-to Analysis Using S park ....Pages 153-169 Effective Inline-Threaded Interpretation of Java Bytecode Using Preparation Sequences....Pages 170-184 Integrating Generations with Advanced Reference Counting Garbage Collectors....Pages 185-199 The Interprocedural Express-Lane Transformation....Pages 200-216 Automatic Detection of Uninitialized Variables....Pages 217-231 Generalised Regular Parsers....Pages 232-246 Rapid and Robust Compiler Construction Using Template-Based Metacompilation....Pages 247-261 The Verifying Compiler: A Grand Challenge for Computing Research....Pages 262-272 Address Register Assignment for Reducing Code Size....Pages 273-289 Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms....Pages 290-302 Integrating High-Level Optimizations in a Production Compiler: Design and Implementation Experience....Pages 303-319 Improving Data Locality by Chunking....Pages 320-334 Compiler Construction: 12th International Conference, CC 2003 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2003 Warsaw, Poland, April 7–11, 2003 Proceedings Author: Görel Hedin Published by Springer Berlin Heidelberg ISBN: 978-3-540-00904-7 DOI: 10.1007/3-540-36579-6 Table of Contents: Combined Code Motion and Register Allocation Using the Value State Dependence Graph Early Control of Register Pressure for Software Pipelined Loops Register Allocation by Optimal Graph Coloring A Compilation and Optimization Model for Aspect-Oriented Programs A Pattern Matching Compiler for Multiple Target Languages A New One-Pass Transformation into Monadic Normal Form Run-Time Type Checking for Binary Programs Precision in Practice: A Type-Preserving Java Compiler The MAGICA Type Inference Engine for MATLAB ® Dimensions of Precision in Reference Analysis of Object-Oriented Programming Languages Polyglot: An Extensible Compiler Framework for Java Scaling Java Points-to Analysis Using Spark Effective Inline-Threaded Interpretation of Java Bytecode Using Preparation Sequences Integrating Generations with Advanced Reference Counting Garbage Collectors The Interprocedural Express-Lane Transformation Automatic Detection of Uninitialized Variables Generalised Regular Parsers Rapid and Robust Compiler Construction Using Template-Based Metacompilation The Verifying Compiler: A Grand Challenge for Computing Research Address Register Assignment for Reducing Code Size An important problem encountered by compiler designers is the phase ordering problem, which can be phrased as "in which order does one schedule the register allocation and code motion phases to give the best target code?".