Cognitive Technology: Instruments of Mind: 4th International Conference, CT 2001, Warwick, UK, August 6-9, 2001 (Lecture Notes in Computer Science, vol. 2117) (Lecture Notes in Computer Science, 2117)

Cognitive Technology: Instruments of Mind Cognitive Technology is the study of the impact of technology on human cog- tion, the externalization of technology from the human mind, and the pragmatics of tools. It promotes the view that human beings should develop methods to p- dict, analyse, and optimize aspects of human-tool relationship in a manner that respects human wholeness. In particular the development of new tools such as virtual environments, new computer devices, and software tools has been too little concerned with the impacts these technologies will have on human cog- tive and social capacities. Our tools change what we are and how we relate to the world around us. They need to be developed in a manner that both extends human capabilities while ensuring an appropriate cognitive t between organism and instrument. The principal theme of the CT 2001 conference and volume is declared in its title: Instruments of Mind. Cognitive Technology is concerned with the interaction between two worlds: that of the mind and that of the machine. In science and engineering, this - teraction is often explored by posing the question: how can technology be best tailored to human cognition? But as the history of technological developments has consistently shown, cognition is also fashioned by technology. Technologies as diverse as writing, electricity generation, and the silicon chip all illustrate the profound and dynamic impact of technology upon ourselves and our conceptions of the world. Intelligent Memory Systems Preface Table of Contents A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro 1. Introduction 2. Concept of the Hybrid Wave Pipeline 3. Analysis of Latency and Cost of Multi-banked DRAM 4. Data Bus Design Options 4-1. Fully Synchronous and Asynchronous Bus 4-2. Hybrid Scheme Based on Dedicated Clock Wave-Pipeline 4-3. Hybrid Circuit and Stage Operation 4-4. Comparison of Bandwidth and Latency 4-5. Taking Advantage of the Latency Difference between Banks 5. Embedded Macro Architecture 5-1. 64Mbit Macro Architecture 5-2. Four-Tile Configuration on a Single Chip 6. Conclusion 7. Acknowledgements References Software Controlled Reconfigurable On-Chip Memory for High Performance Computing 1 Introduction 2 SCIMA 2.1 Overview 2.2 Address Space 2.3 Data Transfer Among Memory Hierarchy 2.4 Recon.guration of On-Chip Memory and Cache 2.5 Other Architectural Issues 2.6 Benefit of On-Chip Memory 3 Optimization of Benchmarks 3.1 NPB Kernel CG 3.2 NPB Kernel FT 3.3 QCD Computation 4 Performance Evaluation 4.1 Evaluation Environment 4.2 Assumptions for the Evaluation 4.3 Classification of Execution Cycles 5 Evaluation Result 5.1 Result 5.2 Discussion 6 Related Works 7 Concluding Remarks Acknowledgment References Content-Based Prefetching: Initial Results 1 Introduction 1.1 Overview 2 Proposed Prefetching Scheme 2.1 Brief Overview 2.2 Trigger Mechanism 2.3 Prediction Mechanism 2.4 Recursive Scan 2.5 Data Movement 3 Workload Characteristics 3.1 Synthetic Benchmark 3.2 Olden Benchmark Suite 3.3 Summary 4 Preliminary Results 4.1 Metrics 4.2 Simple Memory Model 4.3 Synthetic Benchmark 4.4 Olden Benchmarks 4.5 Prefetch Distances 5 Related Work 5.1 Software Based Prefetching 5.2 Hardware Based Prefetching 5.3 Hybrid Prefetching 6 Conclusions and Future Work References Memory System Support for Dynamic Cache Line Assembly 1 Introduction 2 Related Work 3 Impulse Architecture 4 Design 4.1 Scatter/Gather through An Indirection Vector 4.2 Dynamic Cache Line Assembly 5 Performance Evaluation 5.1 Simulation Environment 5.2 Results 6 Conclusions and Future Work References Adaptively Mapping Code in an Intelligent Memory Architecture 1 Introduction 2 Intelligent Memory Architecture 3 Modulles and Partitioning 4 Adaptive & Overlapped Execution 5 Evaluation Setup 6 Evaluation Results 7 Conclusions 8 Acknowledgements References The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems 1 Introduction and Motivation 2 Benchmarks 3 PIM Technology and Architecture 4 Simulation Methodology 5 Metrics 6 Working Set Critical Mass 6.1 Caches 6.2 Paged Memory 7 Mobile Threads 7.1 Execution Model 7.2 Data Layout 7.3 Run Length Experimentation 7.4 Look-Back Reference Results 8 Conclusions and Future Work References Memory Management in a PIM-Based Architecture 1 Introduction 2 Overview of Memory Model and Addres Translation 2.1 Address Translation for Locally Mapped Data 2.2 Translating Remote Addresses 2.3 Parcels 3 Overview of Memory Management 4 Memory Allocation: Virtual vs. Physical 4.1 Virtual Memory Allocation 4.2 Physical Memory Allocation 4.3 Mapping Existing Objects to PIM Global Segments 5 Paging 6 Contexts and Swapping 6.1 Contents of Context 6.2 Swapping 7 Local and Global Segments 7.1 Large Global Segments 7.2 Assigning Names to Global Segments 7.3 Sharing Global Segments across PIMs 8 Summary and Conclusion References Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler 1 Introduction 2 Overview of the VIRAM Architecture 2.1 The Instruction Set 2.2 The VIRAM Processor 3 Compiler Overview 4 On-chip Memory Bandwidth 5 Narrow Data Types 6 Related Work 7 Conclusions References FlexCache: A Framework for Flexible Compiler Generated Data Caching 1 Introduction 2 FlexCache Runtime System 3 FlexCache Compiler 5 Experiments 6 Conclusions and Future Work References Aggressive Memory-Aware Compilation 1 Introduction 2 Related Work References Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips 1 Introduction 2 Memory Hierarchies for PIM Chips 3 Evaluation Environment 4 Evaluation 5 Discussion References SAGE: A New Analysis and Optimization System for FlexRAM Architecture 1 Introduction 2 Intelligent Memory Architecture 3 System Organization 3.1 Statement Splitting 3.2 Wavefront Generating and Scheduling 4 Example 5 Experimental Results 6 Conclusion References Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems 1 Introduction 2 Variable Line-Size Cache Architectures 2.1 Concept 2.2 Statically Variable Line-Size Cache 2.3 Dynamically Variable Line-Size Cache 3 Evaluations 3.1 Cache-Access Time and Energy 3.2 Cache-Miss Rate 3.3 Main-Memory-Access Time and Energy 3.4 Performance/Energy Efficiency 4 Conclusions References The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems 1 Introduction 1.1 Overview of DIVA System Architecture 1.2 Simulation 1.3 Emulation 2 The DIVA Emulator 2.1 Physical Implementation 2.2 Operation 3 Summary and Conclusion 4 References Compiler-Directed Cache Line Size Adaptivity 1 Introduction 2 System Organization 3 Experimental Infrastructure 3.1 Simulator 3.2 Compilation 4 Experiments 5 Conclusions and Future Work References Summary of Question/Answer Sessions for Workshop Presentations 1 Memory Technology 2 Processor and Memory Architecture 3 Applications and Operating Systems 4 Compiler Technology 5 Open microphone Author Index Cognitive Technology: Tool Or Instrument? / Barbara Gorayska, Jonathan P. Marsh And Jacob L. Mey -- Natural-born Cyborgs? / Andy Clark -- Fact And Artifact: Reification And Drift In The History And Growth Of Interactive Software Systems / Martin Loomes And Chrystopher L. Nehaniv -- Thinking Together In Concept Design For Future Products -- Emergent Features For Computer Support / Tuomo Tuikka And Kari Kuutti -- The Space Of Cognitive Technology: The Design Medium And Cognitive Properties Of Virtual Space / Frank Biocca -- Can Social Interaction Skills Be Taught By A Social Agent? The Role Of A Robotic Mediator In Autism Therapy / Iain Werry, Kerstin Dautenhahn And Bernard Ogden / [and Others]. Meurig Beynon, Chrystopher L. Nehaniv, Kerstin Dautenhahn, Eds. Includes Bibliographical References And Index.