Challenger: A LitRPG Adventure (Tower Book 7)

Preface Acknowledgments Contents About the Editor Section Editors Contributors Part I Single Core Processors 1 Microarchitecture Contents Introduction Single-Cycle Processor Design Processor Data Path Processor Control Unit Pipelining Pipeline Principle and Performance Metrics Pipelined Processors Pipeline Hazards Data Hazards Control Hazards Structural Hazards Multiple-Issue Processor Conclusions References 2 The Architecture Contents Introduction Terms and Notations Laws and Models in Microprocessor/System-on-Chip (SoC) Architectures ISA Selection and Considerations CISC: Complex Instruction Set Computer The Baseline: Looking at the ISA of the 8088 and the 8086 Processors IA32 Architectures Extending the Architecture to 64 Bits (X86-64 ISA) IA-64 Registers Adjusting the Architecture to Support New Technologies Summary RISC: Reduced Instruction Set Computer MIPS SPARC ISA ARM: Advanced RISC Machines ARM7-32 Bits AA64 Architecture Summary of ARM ISA The RISC-V Approach for ISA RISCV: Basic ISA (RISCV 2021) RISCV: Extensions (RISCV 2021) Extension M: Integer Multiplication and Division Extension A: Atomic Instructions Extension F: Single-Precision Floating Point Summary of ISA Selection Vector and SIMD Extensions SIMD Architectures MMX Streaming SIMD Extensions (SSE) Advanced Vector Extensions (AVX) Support for Machine Learning Discussion on the Use of SIMD Operations (in Intel's Cores) Support for Vectors Cross-Layers Optimizations Background Delayed Branch in MIPS The User-Defined Microcode Programming VLIW Architectures HW/SW Codesign: The CUDA Approach ISA Agnostic Systems The Use of Intermediate Representations Binary Translation Summary References 3 Architectures for Self-Powered Edge Intelligence Contents Evolution of Edge Intelligence and a Pathway to Self-Powered IntelligentComputations Architectures for Energy Harvesting in IoT Edges A Self-Powered Image Sensor System with Autonomous Mode Management (AMM) Factors Affecting Self-Power Performance Effects of a Processing Pipeline Effects of Unit Pixel Size Effects of SRAM Leakage Energy Effects of Power Converter Efficiency ROI-Aware Image Processing Architecture Moving Object Detection Architecture Low-Power Moving Object Detection Noise-Robust Moving Object Detection ROI-Based Coding Architecture Temporal ROI-Based Coding Spatial ROI-Based Coding Resource-Aware Control of Target Data Rate Conventional Target Data Rate Control Energy- and Content-Aware Target Data Rate Control Resource-Aware Control of Encoding Data Rate Challenges in Data Rate Control Low-Power Data Rate Control Architectural Support for Handling Sparsity in IoT Devices Approaches in Matrix Multiplication Inner Product-Based Approach Outer Product-Based Approach Compressed Sparse Formats Recent Hardware Architecture for Handling Sparsity Hardware Architecture for Inner Product Approach Hardware Architecture for Outer Product Approach Architectures for Power-Gating-Based Active Leakage Control Overview of Power-Gating Challenges and Trade-Offs in Power-Gating Power-Gating Efficiency Learner Self-Adaptive Power-Gating Architecture Test Chip and Measurement Results Conclusion and Future Roadmap References 4 Real-Time Scheduling for Computing Architectures Contents Real-Time Operating System (RTOS) Introduction to Key OS Features Introduction to Real-Time Systems Real-Time CPU Scheduling Scheduling on Single-Core CPUs Scheduling on Multi-core CPUs Real-Time Scheduling for CPU-GPU Systems GPU Background GPU Hardware Architecture Threading Model Scheduling Tasks on a Single GPU Intra-SM Resource Allocation Inter-SM Resource Allocation Memory Transfer Between Device and Host Multi-GPU and CPU-GPU Scheduling Multiple GPUs Controlled by One Host Heterogeneous Systems as DAGs Splitting Tasks Between CPUs and GPUs Application Domains Graphics Processing Cloud Systems Tools and Frameworks NVIDIA and CUDA AMD and ROCm OpenCL Alternative Architectures Processing in Memory FPGAs as Accelerators Real-Time Edge Computing Systems Introduction to Edge Computing The Edge Architecture Real-Time Edge Computing Resource Allocation in Real-Time Edge Contention Model Tiered Architecture Model Parameters Introduction to Real-Time Networks Real-Time Wired Networks Real-Time Wireless Networks Real-Time Flow Routing and Scheduling in Real-Time Wireless Sensor Networks RAP Routing Protocol SPEED Routing Protocol Summary References 5 Secure Processor Architectures Contents Introduction Modern CPU Microarchitecture Micro-architectural Attacks Transient Micro-architectural Attacks Meltdown and Spectre-Like Attacks Micro-architectural Data Sampling Attacks Countermeasures Prevention-Based Countermeasures Detection-Based Countermeasures Conclusions References 6 Bus and Memory Architectures Contents Introduction SoC Overview Processor Overview CPU Types Balanced Processor Architectures CPU Memory Parallelism MSHRs Memory-Level and Memory Hierarchy Parallelism (MLP and MHP) Parallelism to DRAM Accelerators On-Chip Connectivity Interconnect Interfaces Interconnect Topologies Off-Chip Connectivity Summary and Conclusion References Part II Application-Specific Processors 7 Architectures for Multimedia Processing: A Cross-Layer Perspective Contents Introduction and Overview of Video Codecs High Efficiency Video Coding Overview of the Standard Analysis of Computational Complexity, Memory Requirements, and Processor Temperature Hardware and Software Architectures for Video Coding Complexity Reduction Low-Power Memory Architectures Workload Balancing for Multiple Video Tiles Dynamic Thermal Management for HEVC Future Directions Conclusions References 8 Post-Quantum Cryptographic Accelerators Contents Introduction Post-Quantum Cryptography (PQC) NIST Post-Quantum Cryptography Standardisation Project Initial Submissions NIST's PQC Round1 NIST's PQC Round2 NIST's PQC Round3 Classes of Post-Quantum Cryptography Code-Based Multivariate-Based Hash-Based Isogeny-Based Lattice-Based Lattice-Based Cryptography Primitives Lattices Computational Problems on Lattices Average-Case Problems on Standard Lattices Classes of Lattices Ring-LWE Based PKE Scheme Computationally Intensive Components of LWE (and Variants) Discrete Gaussian Sampling Polynomial Multiplication Schoolbook Algorithm Number Theoretic Transform (NTT) Barrett's Reduction Coprocessors for the Lattice-Based Cryptography General Optimisation Strategies Performance Benchmarks Coprocessors Design Paradigms for Lattice-Based Cryptography Optimization Strategies for Implementation of Underlying Components Discrete Gaussian Sampling Polynomial Multiplication Physical Protection of Lattice-Based Cryptography Timing Attacks Power Analysis Attacks Fault Attacks Challenges in the Post-Quantum Cryptography Adaptation Conclusions References 9 Fault Tolerant Architectures Contents Introduction Faults, Errors, and Failures Fault Model Fault Mechanisms External Faults Aging/Stress-Induced Faults Fault Masking Reliability Types of Reliability Reliability Estimation Fault Tolerance Fault Tolerance Activities Redundancy Fault-Tolerant Computation Single-Core Computing Multicore Computing Reconfigurable Computing Fault-Tolerant Memory/Storage Cache/On-chip SRAM Main Memory/DRAM Storage Fault-Tolerant On-Chip Communication Cross-Layer Reliability Domain-Specific Fault Tolerance Signal Processing Wireless Communication Fault Tolerance in Emerging Technologies Emerging Memory Technologies Reliability Issues in NVMs Read Disturb Issue in OxRRAM Thermal Issues due to PCM's High Voltage Operations Fault Tolerance in AI/ML Built-In Error Tolerance of Machine Learning Models Fault Tolerance via Self-Repair Conclusion Glossary References 10 Architectures for Machine Learning Contents Introduction Architectures for Neuromorphic Computing Biological Computing Models and Learning Methods Microarchitecture for Neuromorphic Computing Circuit-Level Design Considerations Prominent Neuromorphic Chips SpiNNaker Neurogrid BrainScales LaCSNN TrueNorth Loihi ODIN Tianjic Architectures for Artificial Neural Networks Design Metrics for ANN Architectures Design Abstractions and Trade-Offs Selective ANN Architectures and Circuits Architectures for Classic Machine Learning Conclusions References 11 Computer Arithmetic Contents Introduction Definitions Radix Positional Notation Absolute Error Relative Error Numerical Precision Units in the Last Place Machine Epsilon Floating-Point Operations Per Second Integer Arithmetic Gray Code Unary Code Fixed-Point Arithmetic Floating-Point Arithmetic IEEE 754 Subnormal Numbers Exceptions Not a Number-NaN and Infinity Quiet NaN Signaling NaN Rounding Modes Floating-Point Approximate Circuits Posit Arithmetic Other Formats BF16 TensorFlow-32 Hardware Implementations Adders Ripple-Carry Adder Carry-Lookahead Adder Multipliers Dividers Square Root Conclusion References 12 Architectures for Scientific Computing Contents Introduction Definitions Scientific Computing Multicore Architectures Manycore Architectures Field-Programmable Gate Arrays Coarse-Grained Reconfigurable Architectures Custom Architectures Multicore Architectures General Purpose Graphics Processing Units Field-Programmable Gate Arrays Coarse-Grained Reconfigurable Architectures Conclusion References Part III Multicore and Reconfigurable Architectures 13 Field-Programmable Gate Array Architecture Contents Introduction Methodology and Tools for FPGA Architecture Evaluation Key FPGA Applications Programmable Logic Blocks Programmable Routing Programmable IO Programmable Clock Distribution Networks On-chip Memory DSP Blocks Processor Subsystems System-Level Interconnect: Network-on-Chip Interposers Configuration and Security Conclusion References 14 Coarse-Grained Reconfigurable Array (CGRA) Contents Introduction Historical Context Architecture: A Landscape of Modern CGRA Compilation for CGRAs Modulo Scheduling and Modulo Routing Resource Graph (MRRG) CGRA Mapping Approaches Heuristic Approaches Mathematical Optimization Techniques Graph-Theory-Inspired Techniques Other Compilation-Related Issues Challenges Related to Data Access Nested Loop Mapping Application-Level Mapping Handling Loops with Control Flow Scalable CGRA Mapping Conclusions References 15 Dynamic and Partial Reconfiguration of FPGAs Contents Introduction FPGA Configuration Designing Partially Reconfigurable Systems Managing Partial Reconfiguration Applications of Dynamic Partial Reconfiguration Computing Infrastructure and Virtualization Design Compilation Adaptive Systems Machine Learning Reliability and Harsh Environments Research Directions Conclusions References 16 GPU Architecture Contents Introduction Graphics Pipeline GPU for General-Purpose Computing Execution Model Programming Interface Hardware Architecture Shader Pipeline Register File Warp Scheduler SIMT Stack Memories Global Memory Constant Memory and Texture Memory Shared Memory L1 and L2 Caches Optimization Use Case: Access-Aware Variable Mapping to Memory Recent Research on GPU Architecture Performance Hiding Memory Access Latency with Advanced Warp Schedulers Throttling Memory Access Latency Energy Efficiency Revisiting Compute Cores and Pipeline Revisiting Register File Reliability Run-Time Error Detection and Correction Fault Analysis Conclusion References 17 Power Management of Multicore Systems Contents Introduction Power Dissipation in Multicore Systems Causes and Effects of Power Dissipation Power Dissipation in Multicore Systems Common Power Reduction Methods Hardware Firmware Dynamic Voltage and Frequency Scaling (dvfs) Dynamic Power Management (dpm) Virtualization Software Task Migration Task Scheduling Data Forwarding Power Management: Embedded Systems Energy Minimization Thermal Management Reliability Improvement Power Management: Desktop and Servers ACPI Standard Power Schemes: Governors Power Management: High-Performance Computing (HPC) Data Centers Fast Heuristics Heuristics Using Design-Time Profiling Machine Learning Network Technologies Recent Advances in Multicore Power Management 2.5D/3D Systems Cross-Layer Approach Emerging Technologies AI-/ML-Based Power Management Conclusion Glossary References 18 General-Purpose Multicore Architectures Contents Introduction Motivating the Need for Concurrent Processing Classifying Parallel Computing Hardware Multiprocessing Thread-Level Parallelism Within an Application What to Do With All These Transistors? Multicore CPU Hardware Design Optimizing CPU Cores for Parallelism Sharing Caches and Main Memory Coordinating Memory Requests Across Cores Scaling to Many Cores Managing Memory Shared-Memory Model Main Memory Policies Mitigating Interference Cache Coherence Memory Consistency Models Optimizing Operating Systems for Multicore CPUs Evaluating Multicore CPUs The Evolution of Multicore CPUs Systems-on-Chip Heterogeneous CPU Cores Chiplet-Based Multicore Design Conclusion References Part IV Emerging Computing Architectures 19 Compute-in-Memory Architecture Contents Introduction DNN Basics and Corresponding CIM Principle Architecture and Algorithm Techniques for CIM Hierarchical Architecture of CIM Network Mapping Strategies Mapping Methods for Inference Mapping Method for Training Number Representation in CIM Architecture Pipeline Design in CIM Architecture Intra-Layer Pipeline Inter-Layer Pipeline Quantization Techniques in CIM Architectures Hardware Implementations for CIM Architecture Device Technologies SRAM Two Terminal eNVM Three-Terminal eNVM Overcoming the Non-idealities from eNVM Circuit Techniques for CIM Memory Modification Input Encoding Output Sensing Frameworks for Evaluating CIM Designs Conclusion References 20 Design Automation Techniques for Microfluidic Biochips Contents Introduction Flow-Based Microfluidic Biochips Design Tasks for FBMBs Architecture Design of the Flow Layer Architecture Design of the Control Layer Design Automation for FBMBs Synthesis Methods for the Flow Layer Synthesis Methods for the Control Layer Synthesis Methods for the Codesign of the Control and Flow Layers Digital Microfluidic Biochips Technology Platforms and Applications Synthesis Methods Scheduling and Module Placement Droplet Routing MEDA Biochips Hardware Implementation MEDA Evolution Synthesis Methods Scheduling and Placement for MEDA Biochips Droplet Routing and Extension for MEDA Conclusion References 21 Architectures for Quantum Information Processing Contents Introduction Background Quantum Bits (Qubits) Quantum Gates Quantum Error Gate Error Relaxation and Dephasing Measurement Error Crosstalk Error Quantum Hardware Qubit Technologies Superconducting Qubits Trapped-Ion Qubits Spin Qubits Quantum Algorithms Algorithms Designed for Fault-Tolerant Quantum Computers Shor's Algorithm Grover's Algorithm Algorithms for NISQ Computers Variational Quantum Eigensolver or VQE Quantum Approximate Optimization Algorithm or QAOA Quantum Software Quantum Program, Quantum Instruction Sets, and Software Development Kits Quantum Programming Languages Quantum Annealing Compilation, Mapping, and Optimization Superconducting Quantum Computers Coupling Constraints and Need for SWAP Operation Compilation and Optimization Trapped-Ion Quantum Computers Shuttle Operation Compilation and Optimization Considerations for Noisy Systems Technology Agnostic Work Noise-Aware Qubit Mapping Measurement Error Mitigation Superconducting-Specific Work Crosstalk Mitigation Leveraging Extended Native Gates Application-Specific Compilation Conclusion References 22 Design and Tool Solutions for Monolithic Three-Dimensional Integrated Circuits Contents Introduction Monolithic 3D IC Design Flow Motivation and Background Benefit Trends of Monolithic 3D ICs Across Technology Nodes Analysis on Benefits of Monolithic 3D ICs Technology Nodes and Design Libraries Implementation Methodology Power Saving Trend of Monolithic 3D ICs Analysis of Trends M3D Power Saving at Low Frequency M3D Power Saving at High Frequency A Design-Aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools Implementation Methodology Design-Aware Partitioning Stage MIV Planning Stage Cascade-2D Stage Impact of New Monolithic 3D IC Design Flow Power and Performance Benefit Comparison to Shrunk-2D Design Flow Power Supply Integrity of Monolithic Three-Dimensional Integrated Circuits Motivation and Background System-Level Power Delivery Network Analysis for Monolithic 3D ICs System-Level Power Delivery Network Modeling Analysis on Power Supply Integrity of Monolithic 3D ICs Monolithic 3D IC Power Delivery Network Design Flow Technology Nodes and Design Libraries Analysis Methods Static Rail Analysis Dynamic Rail Analysis Frequency- and Time-Domain Analysis Monolithic 3D ICs for Deep Neural Network Hardware Motivation and Background Impact of Monolithic 3D ICs on On-Chip Deep Neural Networks Targeting Speech Recognition Deep Neural Network for Speech Recognition DNN Topology Deep Neural Network Training and Classification Coarse-Grain Sparsification Deep Neural Network Architecture Description Impact of Monolithic 3D ICs on Energy-Efficiency of Deep Neural Network Hardware Area, Wire-Length, and Capacitance Comparisons Power Comparisons Impact of Monolithic 3D ICs on Performance of Deep Neural Network Hardware Architectural Impact Discussions CGS-16 and CGS-64 Architecture Comparisons Impact of Workloads Conclusion References Part V Processor Design and Programming Flows 23 Architecture Description Languages Contents Introduction A Brief History of ADLs The Classical Era: 1990–2000 The First Industrial Era: 2000–2010 The Second Industrial Era: 2010–2020 Types and Characteristics of ADLs Types of ADLs Characteristics of ADLs Key ADLs MIMOLA EXPRESSION nML LISA PEAS TENSILICA TIE ARC APEX Codasip CodAL Andes ACE RISC-V Chisel ADL-Driven Methodologies Generation of Software Tools Automatic Synthesis of Custom Instructions for an Application Instruction-Set Simulator Generation Generation of Hardware Implementation Top-Down Verification Validation of an ADL Specification Specification-Driven, Simulation-Based, Verification Applications of ADL-Based Design Conclusions References 24 Accelerator Design with High-Level Synthesis Contents Introduction Background: Technology and Models Target Technology Accelerator Models Accelerator Template Introduction to High-Level Synthesis A Traditional High-Level Synthesis Framework A Bit of History on Commercial Products and Academic Projects From Input Specification to Intermediate Representation Input Specification and Intermediate Representation Analysis and Optimization of the Intermediate Representation Creation of the Microarchitecture Scheduling and Performance Optimization Binding and Resource Optimization Definition of the Memory Architecture Creation of the FSM Controller RTL Generation and System Integration Code Generation, Evaluation, and Verification System-Level Integration and Optimization Open and Modern Challenges Creation of Domain-Specific Architectures Programmability and System-Level Optimization Hardware Security and Data Protection Conclusion References 25 Processor Simulation and Characterization Contents Introduction Application and Algorithm Analysis Data Types and Operations Algorithms Example: Affine Transform of 2D Image New or Existing Processor? Existing Processor Extending Configurable Processor New Processor with New ISA Hybrid Mode: New ISA with Custom Extensions Standard Benchmarks Issues with Estimating Processor Performance Whetstone Linpack Dhrystone CoreMark Embench SPEC CPU EEMBC Berkeley Design Technology Summary Using Application Code for Benchmarking Estimation Analysis Examples of Estimation Flow Hardware Aspects Software Aspects Custom Instructions For Further Consideration Processor Simulation Functional Simulation Definition Trace-Driven Cache Simulators and Branch-Prediction Simulators Instruction Mix Analysis Instruction Level Parallelism (ILP) Memory Access Patterns Register-File Usage Analysis Open-Source Simulators Cycle-Level Simulation Definition Performance Analysis Metrics and System Partitioning Optimization Configurability Open-Source Simulators Hardware Emulation Definition Emulation Modes Using Processor Simulators in System Modelling Summary Table Comparing Various CPU Modelling Abstractions Examples Conclusion References 26 Methodologies for Design Space Exploration Contents Introduction DSE: The Basic Concepts Two Basic Ingredients of DSE Y-Chart-Based DSE Evaluation of a Single Design Point Simulative Fitness Evaluation Analytical Fitness Evaluation Searching the Design Space GA-Based DSE Optimizing GA-Based DSE Multi-application Workload Models Scenario-Based DSE Application Exploration NAS by Means of Evolutionary Piecemeal Training (EPT) Evolutionary Operators NAS Results Conclusion and Outlook References 27 Virtual Prototyping of Processor-Based Platforms Contents Introduction to Virtual Prototypes SoC Design and Verification Overview Historic Background of Virtual Prototyping Virtual Prototyping in the Verification Continuum Use-Cases for Virtual Prototypes Architecture Analysis Macro-architecture Specification HW/SW Performance Optimization and Validation Software Use-Cases Early Software Development Software Regression Testing Hybrid Use-Cases for Software-Driven Functional Verification RTL Co-simulation Hybrid Emulation Hybrid FPGA Prototyping System-Level Power Analysis Summary Building Transaction Level Virtual Prototypes The SystemC Transaction Level Modeling Standard Loosely Timed Modeling Style Extended Loosely Timed Modeling Style Approximately Timed Modeling Style Extended AT TLM-2.0 Summary Building TLM Components for Virtual Prototypes Levels of Abstraction Processor Models TLM Integration of Processor Models TLM Models of Peripheral Components SSD Controller SoC Case Study SSD Controller SoC Introduction Loosely Timed Virtual Prototype of the SSD SoC Accurate Virtual Prototype of SSD SoC SSD Case Study Summary Conclusion and Outlook References 28 FPGA-Specific Compilers Contents Introduction Existing HLS Compilers and Programming Models C-Based HLS Tools Dataflow Compilers Domain-Specific Languages (DSLs) Emerging Accelerator Design Languages Key Compiler and Synthesis Optimizations Pipelining Techniques Operator-Level Optimizations Statically Scheduled Pipelining Dynamically Scheduled Pipelining Parallelization Techniques Homogeneous Data-Level Parallelism Heterogeneous Task-Level Parallelism Memory Customization Techniques Exploiting Data Reuse Decoupled Access-Execute Data Vectorization Memory Banking Data Type Customization Techniques Automatic Bitwidth Optimization Custom Precision Floating-Point Data Types Float to Fixed-Point Conversion Case Study: Binarized Convolutional Neural Networks Algorithm Overview Pipelining and Unrolling Line Buffers and Window Buffers Data Vectorization Building the BNN Accelerator Using HeteroCL Evaluation Concluding Remarks References 29 Approximate Computing Architectures Contents Approximate Computing Approximate Arithmetic Components Design Methodologies for Approximate Components Manual Approximation Methods Automated Approximation Methods Error Metrics and Evaluation Analysis for Approximate Components Arithmetic Error Metrics General Error Metrics Quality Evaluation Design Methods for Building Approximate Hardware Accelerators: Case Studies for Error-Tolerant Applications Image and Video Processing Applications AutoAx Methodology Results Deep Neural Networks (DNNs) ALWANN Methodology Evaluation and Experiments Cross-Layer Approximations for Error-Tolerant Applications Methodology for Combining Hardware- and Software-Level Approximations Cross-Layer Methodology for Optimizing DNNs Case Studies for Improving the Energy and Performance Efficiency of DNN Inference Structured Pruning Quantization Hardware-Level Approximations: Impact of Self-Healing and Nonself-Healing Designs on DNN Accuracy Conclusions References 30 Parallel Programming Models Contents Introduction Hardware Models Constructs in Parallel Programming Models Taxonomy The OpenMP Programming Model The Worksharing Model The Tasking Model SIMD Support in OpenMP Vectorization, Intrinsics, and Semi-automatic Vectorization SIMD Loops Function Vectorization The Accelerator Model The OmpSs-2 Programming Model Advanced Dependency System Global Domain of Dependencies Advanced Dependency Types Exploiting Structured Parallelism on Many-Core Processors Optimal Task Granularity Work-Sharing Task Syntax Semantics of Work-Sharing Tasks OmpSs-2 NUMA Support NUMA-Aware Allocation API Nanos6 Data-Tracking System Nanos6 NUMA-Aware Scheduling System The XiTAO Programming Model and Runtime Explicit DAG Programming in XiTAO Software Topologies and Locality-Aware Programming The Software Topology Mapping Locality-Aware Moldable Mapping The XiTAO Data-Parallel Interface The Asynchronous Data-Parallel Mode The Synchronous Data-Parallel Mode The XiTAO Runtime XiTAO Internals Configuring the Runtime Conclusion References 31 Dataflow Models of Computation for Programming Heterogeneous Multicores Contents Introduction About Models of Computation Dataflow Models of Computation Static Dataflow Models Homogeneous Synchronous Dataflow (HSDF) Synchronous Dataflow (SDF) Further Static Extensions Dynamic Dataflow moc Kahn Process Network Dataflow Process Networks Relation to Other Dataflow MoCs and Extensions Reconfigurable Dataflow πSDF Other Reconfigurable Dataflow moc Optimization of Dataflow Programs Modeling Heterogeneous Platforms System-Level Description Modeling Performance and Energy Consumption Static Mapping Hybrid Mapping Examples: Models and Tools Dataflow in Commercial and Mainstream Tools MPSoC Application Programming Studio (MAPS) Preesm and Spider Preesm Spider Conclusion and Outlook References 32 Retargetable Compilation Contents Introduction and Historical Perspective Compiler Construction Compiler Frameworks Retargetable Compilers Outline of This Chapter Anatomy of a Compiler Intermediate Representations Compilation Phases and Dependencies Front End Middle End Back End Linker Architectural Scope of ASIPs Parallelism Specialization Example Retargetable Compilers for ASIPs Processor Intermediate Representations Retargetable Compiler Optimizations Front End and Middle End Code Selection Register Allocation Register Assignment Instruction Scheduling Conclusions References Part VI Test and Verification 33 Verification and Its Role in Design of Modern Computers Contents Introduction Formal Verification, Simulation, and Emulation Outline of the Section Section Organization Bit-Level Model Checking Algorithms C-to-RTL Equivalence Checking Symbolic Simulation Mechanical Theorem Proving Versatile Binary-Level Concolic Testing Information Flow Analysis Verification of Quantum Circuit Design Flows Discussion Conclusion References 34 Bit-Level Model Checking Contents Introduction Preliminaries Explicit Example: A Simple Counter Linear Time Temporal Logic Representing Systems Symbolically Algorithms for Safety Properties The Induction Principle Overview of Model Checking Algorithms Symbolic Model Checking (with BDDs) Bounded Model Checking k-Induction Interpolation and Model Checking Interpolation Sequence-Based Model Checking (Isb) Interpolation-Based Model Checking (Itp) Property Directed Reachability Combining Interpolation and Pdr Summary Algorithms for Liveness Properties Introduction Overview of Model Checking Algorithms Symbolic Model Checking with BDDs Liveness-to-Safety Conversion (L2S) Bounded Liveness Checking Counter-Based Translation kLiveness FAIR Summary Design Simplification Techniques Reductions Combinational Redundancy Removal Retiming Sequential Redundancy Removal Input Reparameterization Phase Abstraction Over-approximations Proof-Based Abstraction Counterexample-Guided Abstraction Other Approaches Summary Conclusion References 35 High-Level Formal Equivalence Contents Types of Equivalence to Check Combinational Equivalence Sequential Equivalence Transaction-Based Equivalence Verification Methodology Using Design Exercise for Datapath Designs Advanced Datapath Verification Managing Inconclusive Proofs Accuracy Challenges Accuracy Optimized Component Verification Proving Faithful Rounding Proving Monotonicity Proving Commutativity References 36 Verification of Arithmetic and Datapath Circuits with Symbolic Simulation Contents Introduction Symbolic Simulation Symbolic Simulation as Formal Verification Symbolic Simulation Among Formal Verification Methods Chapter Outline Simulation Booleans and Undefined Values Circuit Simulation and Undefined Values Mathematical Model of Circuit Simulation Circuit Properties Mathematical Model of Circuit Properties Symbolic Simulation Symbolic Computation Simulation with Symbolic Values Mathematical Model of Symbolic Simulation Practical Considerations Simulation Scope Control Property Triggers Scope Reduction by Triggers Reachable-State Invariants Complexity Management Simulation Complexity Complexity Analysis Weakening Verification Flow Arithmetic Circuits Direct Verification Floating-Point Operations Floating-Point Addition Integer Multiplication Floating-Point Multiplication and Fused Multiply-Add Floating-Point Division and Square Root Industrial Verification Related Work References 37 Microprocessor Assurance and the Role of Theorem Proving Contents Introduction ACL2 Preliminaries Logic Basics Extension Principles The Theorem Prover Some Execution Features: Guards, MBE, and Stobjs Intended Domains and Guards Must Be Equal Single-Threaded Objects ISA Analysis ISA Formalization Mechanical Analysis for ISA Binary Code Analysis with ISA Models Some Formalized ISAs Analysis of Microarchitecture Properties Pipelining, Out-of-Order, and Speculative Executions Pipelining Interrupts, Out-of-Order and Speculative Execution, Self-Modifying Code, and the Works Reasoning About Memory Hierarchy Verification of Execution Units Deep Dive: Formalization and Analysis of (Simplif