Area Array Interconnection Handbook

Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili­ con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de­ veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects. This handbook provides a comprehensive treatment of area-array interconnections for both chips and microelectronic packages in terms of optimizing densification, functionality and reliability. It provides comparisons with alternative and competing technologies, clearly defining cost versus benefit tradeoffs and strategies. Process details are defined in the order of their typical manufacturing sequence, indicating tooling requirements and potential yield detractors. In addition, the handbook has individual chapters devoted to supporting disciplines that play a key role in satisfying the requirements of microelectronic package applications: efficient thermal-dissipation techniques, metallurgical and mechanical characteristics of interconnections and electrical design strategies. Area-array technology at both die and chip carrier levels offers the best opportunity of satisfying the demanding performance requirements that users at all levels of the product spectrum have come to expect. This handbook fully describes the ̀how and why' of the inherent elements of area-array technology that give rise to enhanced electrical and thermal dissipation capabilities, and densification to accommodate demanding design requirements, while at the same time accommodating size and cost reductions to enhance comfort and portability. This handbook is the only book that provides a complete and integrated treatment which includes all the aspects of area-array microelectronics. Each chapter is self contained, written in a clear, concise, easy-to-understand manner. It sets forth fundamentals followed by the application of those principles making prior knowledge of the subject material unnecessary in order to utilize this reference. The handbook will serve as an excellent text or companion reference for a variety of electronic packaging courses or workshops. FEATURES: describes all the key elements of microelectronic packaging technology; organized into three categories: die, chip carrier, and support technologies; presents information in a clear and concise manner; can be utilized as a textbook or companion reference for a range of microelectronic packaging courses; each chapter is self-contained; provides guidelines and strategies for making microelectronic packaging choices. ABOUT THE EDITORS: Considered ̀pioneers' in the field of microelectronics packaging, Karl Puttlitz and Paul Totta represent 80 years of experience in all aspects of the technology. They were key forces in the definition and implementation of flip-chip technology from its very inception at IBM and through its evolution during the past four decades. As major contributors in the development and manufacture of various microelectronics chip-carrier packages, the authors are frequently invited to speak at universities, international conferences and workshops Front Matter....Pages i-lxviii History of Flip Chip and Area Array Technology....Pages 1-35 Front Matter....Pages 37-37 Wafer Bumping....Pages 39-116 Wafer-Level Test....Pages 117-148 Known Good Die (KGD)....Pages 149-200 Wafer Finishing—Dicing,Picking,Shipping....Pages 201-227 Ceramic Chip Carriers....Pages 228-267 Laminate/HDI Die Carriers....Pages 268-314 Flip-Chip Die Attach Technology....Pages 315-349 Solder Bump Flip-Chip Replacement Technology on Ceramic Carriers....Pages 350-370 Manufacturing Considerations and Tools for Flip Chip Assembly....Pages 371-420 Test and Burn-in Sockets....Pages 421-451 Underfill: The Enabling Technology for Flip-Chip Packaging....Pages 452-499 Reliability of Die-Level Interconnections....Pages 500-548 Front Matter....Pages 549-549 Ceramic and Plastic Pin Grid Array Technology....Pages 551-576 Plastic Ball Grid Array....Pages 577-613 Tape Ball Grid Array....Pages 614-655 Ceramic Ball and Column Grid Arrays....Pages 656-701 Chip Scale Package Technology....Pages 702-761 Assembly of Area Array Components....Pages 762-803 Area Array Component Replacement Technology....Pages 804-837 Front Matter....Pages 549-549 Product Connector Technology....Pages 838-881 Board-Level Area Array Interconnect Reliability....Pages 882-945 Chip Scale Package Assembly Reliability....Pages 946-971 Front Matter....Pages 973-973 Area-array Design Principles....Pages 975-1010 Area Array Leverages: Why and How to Choose a Package....Pages 1011-1030 Interconnections for High-Frequency Applications....Pages 1031-1048 Thermal Performance....Pages 1049-1107 Metallurgical Factors....Pages 1108-1144 Back Matter....Pages 1145-1188