Architecture of Computing Systems : 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13–15, 2022, Proceedings

This book constitutes the proceedings of the 35th International Conference on Architecture of Computing Systems, ARCS 2022, held virtually in July 2022. The 18 full papers in this volume were carefully reviewed and selected from 35 submissions. ARCS provides a platform covering newly emerging and cross-cutting topics, such as autonomous and ubiquitous systems, reconfigurable computing and acceleration, neural networks and artificial intelligence. The selected papers cover a variety of topics from the ARCS core domains, including energy efficiency, applied machine learning, hardware and software system security, reliable and fault-tolerant systems and organic computing. Preface Organization Keynote Talks SpMV: An Embarrassing Kernel for Modern Compute Devices Low-level Fun with Parallel Runtime Systems Contents Energy Efficiency Energy Efficient Frequency Scaling on GPUs in Heterogeneous HPC Systems 1 Motivation, Problem Statement and Key Contributions 1.1 Motivation 1.2 Problem Statement and Key Contributions 2 Related Work and Background 2.1 Performance and Energy Measurement Tools 2.2 Benchmarks 2.3 Energy Efficiency on Graphics Processing Units 3 Methodology 4 Results 4.1 Minimum Interval Length Between Measurements 4.2 Frequency Scaling 4.3 Frequency vs. Total Energy Consumption 5 Summary, Future Research and Conclusion References Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism 1 Introduction 2 Related Work 3 Transport Triggered Architectures 4 Dual-IS Processor 4.1 Instruction Translation 4.2 Micro-operation Sequencing 4.3 Control and Data Hazards 4.4 Mode Switching 5 Evaluation 5.1 Evaluated Designs 5.2 Synthesis Results 5.3 Performance 5.4 Energy Efficiency 5.5 Discussion 6 Conclusions References Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA 1 Introduction 1.1 Reconfigurable Computing 1.2 Related Work 1.3 This Work 2 Instruction Set Architecture 2.1 Fragment Instances 2.2 Local Interaction with Target Instruction Pointers (TIPs) 2.3 Global Interaction of Fragment Instances 2.4 What's the RISC? 3 Programming 3.1 Local Programming 3.2 Global Programming 4 Microarchitecture 4.1 Fragment Instance Management 4.2 Tiles and PEs: Fragment Instances on Fabric 4.3 Dormant Fragment Instances 4.4 Memory Subsystem 5 Evaluation Methodology 6 Results 7 Discussion References Applied Machine Learning Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning 1 Introduction 2 Related Work 3 Motivation, Problem, and Solution Overview 3.1 Motivation: Technology Trends 3.2 Problem Definition 3.3 Solution Overview 4 Modeling and Optimization 4.1 Slowdown Estimation for a Given Job Set and Hardware Setup 4.2 Hardware Setup Optimization for a Given Job Set 4.3 Job Sets Selection 5 Evaluation 5.1 Evaluation Setup 5.2 Experimental Results 6 Conclusion References FPGA-Based Dynamic Deep Learning Acceleration for Real-Time Video Analytics 1 Introduction 2 Overview of the Proposed System 2.1 Neural Network Architecture Search 2.2 Neural Network Model Compilation 2.3 Software and Hardware Run-Time Management 3 DNN Model Optimisation 3.1 Brief Introduction of OFA 3.2 Model Generation and Optimisation 4 System Hardware/Software Co-design 4.1 Hardware Architecture 4.2 Software Implementation 4.3 Communication Between Processes 5 Experiments 5.1 Overall System Setup 5.2 DNN Model Management 5.3 Results and Analysis 6 Time and Power Consumption 6.1 Impact Factors 6.2 Benchmark 7 Conclusion References Advanced Computing Techniques Effects of Approximate Computing on Workload Characteristics 1 Introduction 2 Related Work and Background 3 Our Study 4 Evaluation 4.1 Workload Characteristics 4.2 Details on Application-Level 4.3 Expectations and Observations 4.4 Speedup and Accuracy 5 Conclusions References QPU-System Co-design for Quantum HPC Accelerators 1 Introduction 2 Quantum Max-Cut with QAOA 2.1 The Quantum Approximate Optimisation Algorithm 2.2 Background on Max-Cut and QAOA 2.3 Modelling Max-Cut as QUBO 2.4 Setup 3 Hardware-System Co-design 3.1 Optimisation Potentials 3.2 Parameter Estimation on IBM-Q Hardware 3.3 Physical Possibilities and Limitations 3.4 Variation of the Coupling Density 3.5 Variation of the Backend Size 4 Conclusion and Outlook References Hardware and Software System Security Protected Functions: User Space Privileged Function Calls 1 Introduction 2 Background and Related Work 2.1 Protection Rings and Paging 2.2 System Call and Control Transfer Mechanisms 2.3 Related Work 3 Protected Functions 3.1 Protected Pages 3.2 Privilege Escalation/De-escalation 3.3 Control Transfer Management 3.4 Security Consideration 3.5 Bootstrapping Process 3.6 Implementation 4 Evaluation 4.1 Measurements 5 Conclusion and Future Work References Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs 1 Introduction 2 Background and Previous Work 3 Concept 4 Implementation 4.1 Extraction of LUT Logic Functions from the Bitstream 4.2 Extraction of LUT Logic Functions from the Netlist 4.3 LUT Decomposition 4.4 Boolean Matching 4.5 Core Identification 5 Evaluation 5.1 Revisiting the Ratio Variable 5.2 Experimental Results 6 Conclusion and Future Work References Hardware Isolation Support for Low-Cost SoC-FPGAs 1 Introduction 2 Related Work 3 Isolation Limitations in Low-Cost SoC-FPGAs 4 Proposed Method 4.1 Protection Unit Architecture 4.2 Example 4.3 Validation 5 SoC-FPGA Implementation 6 Results and Discussion 7 Conclusion References Reliable and Fault-Tolerant Systems Memristor Based FPGAs: Understanding the Effect of Configuration Memory Faults 1 Introduction 2 Technical Background 2.1 Related Work 2.2 Memristor Types and Typical Defects 2.3 Configuration Memory with Memristors 2.4 Tool Flow of VTR 3 Lookup Tables 3.1 Impact of Memory Defects 3.2 Modified Tool Flow 3.3 Experimental Setup 3.4 Experimental Results 4 Routing Elements 4.1 Impact of Memristor Defects 4.2 Modified Tool Flow 4.3 Experimental Setup 4.4 Experimental Results 5 Conclusion References On the Reliability of Real-Time Operating System on Embedded Soft Processor for Space Applications 1 Introduction 2 Related Works 3 Background on Radiation-Induced Effect on Reconfigurable Logic 4 Proton Radiation Test-Based Reliability Fault Model 5 The Reliability Analysis Workflow 5.1 The Implemented Hardware/Software Platform 5.2 Fault Injection Analysis 6 Experimental Analysis and Results 7 Conclusions and Future Works References Special Track: Organic Computing NDNET: A Unified Framework for Anomaly and Novelty Detection 1 Introduction 2 Related Work 3 The Library NDNET 3.1 Overview 3.2 mCANDIES 3.3 Detectors 4 Use Cases 4.1 Anomaly Detection in Design Optimization 4.2 Novelty-, Anomaly-Detection in a Motor Test Bench 5 Conclusion and Future Work References Organic Computing to Improve the Dependability of an Automotive Environment 1 Introduction 1.1 Scope 2 Related Work 3 ADNA and AHS Concept 4 Fault Diagnosis 5 Challenges with the Organic Computing Approach 5.1 Accessing Sensors and Actuators 5.2 Development Tools and Simulations 5.3 System Verification 6 Adaption to a Test Platform 6.1 General Autonomous Driving Approach 6.2 Autonomous Driving with Organic Computing 7 Conclusion References A Context Aware and Self-improving Monitoring System for Field Vegetables 1 Introduction 2 Related Work 3 Approach 3.1 Proposed Algorithm 3.2 Experimental Setup 4 Results 5 Discussion 6 Conclusion References Semi-model-Based Reinforcement Learning in Organic Computing Systems 1 Motivation 2 Model-Based and Model-Free Reinforcement Learning 2.1 The Model 2.2 Model-Free Reinforcement Learning 2.3 Model-Based Reinforcement Learning 3 Interpolated Experience Replay 4 Interpolation vs. Approximation 5 Semi-model-Based Reinforcement Learning 6 Interpolation-Based RL in Organic Computing 7 Related Work 8 Conclusions References Deep Reinforcement Learning with a Classifier System – First Steps 1 Introduction 2 Background: The Extended Classifier System 3 Approaches to Neural and Deep LCS 4 Approach: Concepts for a Deep XCS 5 Evaluation 5.1 Experimental Design 5.2 6-RMP Experiments 5.3 Frozen Lake Experiments 5.4 Maze4 Experiments 6 Conclusion References GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization 1 Introduction 2 Background and Related Work 3 Range-Based LCT and Extensions 3.1 LCT Extensions to Enable Accuracy-Based GA 3.2 Exploration-Exploitation Strategy 3.3 States and Actions 3.4 Objective and Reward Function 4 GA-Based Classifier Evolution 4.1 State Space Analysis and Classifier Validity Check 4.2 Covering Operator 4.3 Crossover, Mutation and Subsumption 4.4 Addition and Deletion Strategy 5 Experimental Setup and Results 5.1 Experimental Setup 5.2 Resource Utilization 5.3 Performance 6 Conclusion References Author Index