Application-Specific Integrated Circuits

This comprehensive book on application specific integrated circuits (ASICs) describes the latest methods in VLSI systems design. ASIC design, using commercial tools and predesigned cell libraries, is the fastest, most cost-effective, and least error prone method of IC design. As a consequence, ASICs and ASIC design methods have been increasingly popular in industry for a wide range of applications. The book covers semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design -- design entry, logic synthesis, simulation, and test -- and then to physical design -- partitioning, floorplanning, placement, and routing. You will find in practical, well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and complete your own design. Features: Broad coverage that includes cell-based ICs, gate arrays, field-programmable gate arrays (FPGAs), and complex programmable logic devices (PLDs). Examples, throughout the book, that have been checked with a wide range of commercial tools to ensure their accuracy and utility. Separate chapters and appendixes on both Verilog and VHDL, including material from IEEE standards, that serve as a complete reference for high-level, ASIC-design entry. As in other landmark VLSI books published by Addison-Wesley, the author's teaching expertise and industry experience illuminate the presentation of useful design methods. Any engineer, manager, or student who is working with ASICS in a design project, or who is simply interested in knowing more about the different ASIC types and design styles, will find this book to be an invaluable source, reference, and guide. Intended for engineering students and professional ASIC designers, this comprehensive text examines fundamental ASIC design. It covers custom ASICs, programmable ASICs, logical design and physical design. INTRODUCTION TO ASICs 1 1.1 Types of ASICs 6 1.2 Design Flow 18 1.3 Case Study 20 1.4 Economics of ASICs 23 1.5 ASIC Cell Libraries 31 1.6 Summary 34 1.7 Problems 35 1.8 Bibliography 40 1.9 References 42 CMOS LOGIC 44 2.12 References 125 2.1 CMOS Transistors 48 2.2 The CMOS Process 57 2.3 CMOS Design Rules 67 2.4 Combinational Logic Cells 71 2.5 Sequential Logic Cells 79 2.6 Datapath Logic Cells 84 2.7 I/O Cells 106 2.8 Cell Compilers 109 2.9 Summary 110 2.10 Problems 111 2.11 Bibliography 123 ASIC LIBRARY DESIGN 129 3.1 Transistors as Resistors 131 3.2 Transistor Parasitic Capacitance 135 3.3 Logical Effort 143 3.4 Library-Cell Design 155 3.5 Library Architecture 156 3.6 Gate-Array Design 158 3.7 Standard-Cell Design 164 3.8 Datapath-Cell Design 167 3.9 Summary 169 3.10 Problems 170 3.11 Bibliography 181 3.12 References 182 PROGRAMMABLE ASICs 183 4.1 The Antifuse 185 4.2 Static RAM 189 4.3 EPROM and EEPROM Technology 190 4.4 Practical Issues 192 4.5 Specifications 195 4.6 PREP Benchmarks 197 4.7 FPGA Economics 198 4.8 Summary 203 4.9 Problems 205 4.10 Bibliography 210 4.11 References 211 PROGRAMMABLE ASIC LOGIC CELLS 212 5.1 Actel ACT 213 5.2 Xilinx LCA 227 5.3 Altera FLEX 232 5.4 Altera MAX 233 5.5 Summary 240 5.6 Problems 247 5.7 Bibliography 253 5.8 References 254 PROGRAMMABLE ASIC I/O CELLS 255 6.1 DC Output 257 6.2 AC Output 261 6.3 DC Input 268 6.4 AC Input 274 6.5 Clock Input 279 6.6 Power Input 282 6.7 Xilinx I/O Block 285 6.8 Other I/O Cells 287 6.9 Summary 289 6.10 Problems 291 6.11 Bibliography 301 6.12 References 302 PROGRAMMABLE ASIC INTERCONNECT 304 7.1 Actel ACT 306 7.2 Xilinx LCA 315 7.3 Xilinx EPLD 320 7.4 Altera MAX 5000 and 7000 321 7.5 Altera MAX 9000 322 7.6 Altera FLEX 323 7.7 Summary 325 7.8 Problems 328 7.9 Bibliography 331 7.10 References 332 PROGRAMMABLE ASIC DESIGN SOFTWARE 333 8.1 Design Systems 334 8.2 Logic Synthesis 340 8.3 The Halfgate ASIC 343 8.3.4 Comparison 351 8.4 Summary 352 8.5 Problems 353 8.6 Bibliography 359 8.7 References 364 LOW-LEVEL DESIGN ENTRY 366 9.1 Schematic Entry 368 9.2 Low-Level Design Languages 386 9.3 PLA Tools 395 9.4 EDIF 397 9.5 CFI Design Representation 413 9.6 Summary 417 9.7 Problems 418 9.8 Bibliography 422 9.9 References 423 VHDL 424 10.1 A Counter 426 10.2 A 4-bit Multiplier 427 10.3 Syntax and Semantics of VHDL 433 10.5 Entities and Architectures 437 10.6 Packages and Libraries 440 10.7 Interface Declarations 445 10.8 Type Declarations 449 10.9 Other Declarations 451 10.10 Sequential Statements 456 10.11 Operators 460 10.12 Arithmetic 462 10.13 Concurrent Statements 465 10.14 Execution 471 10.15 Configurations and Specifications 473 10.16 An Engine Controller 475 10.17 Summary 481 10.18 Problems 484 10.19 Bibliography 496 10.20 References 497 IEEE Language Reference Manual project 498 VERILOG HDL 507 11.1 A Counter 509 11.2 Basics of the Verilog Language 511 11.3 Operators 518 11.4 Hierarchy 521 11.5 Procedures and Assignments 523 11.6 Timing Controls and Delay 526 11.7 Tasks and Functions 532 11.8 Control Statements 533 11.9 Logic-Gate Modeling 536 11.10 Modeling Delay 539 11.11 Altering Parameters 542 11.12 A Viterbi Decoder 543 11.13 Other Verilog Features 557 11.14 Summary 564 11.15 Problems 567 11.16 Bibliography 574 11.17 References 576 complete specification of the Verilog HDL 598 LOGIC SYNTHESIS 637 12.1 A Logic-Synthesis Example 640 12.2 A Comparator/MUX 642 12.3 Inside a Logic Synthesizer 648 12.11 Performance-Driven Synthesis 653 12.4 Synthesis of the Viterbi Decoder 659 12.5 Verilog and Logic Synthesis 668 12.6 VHDL and Logic Synthesis 684 12.7 Finite-State Machine Synthesis 701 12.8 Memory Synthesis 708 12.9 The Multiplier 712 12.10 The Engine Controller 718 12.12 Optimization of the Viterbi Decoder 722 12.13 Summary 726 12.14 Problems 727 12.15 Bibliography 739 12.16 References 741 SIMULATION 744 13.1 Types of Simulation 746 13.2 The Comparator/MUX Example 748 13.3 Logic Systems 761 13.4 How Logic Simulation 774 13.5 Cell Models 778 13.6 Delay Models 793 13.7 Static Timing Analysis 800 13.8 Formal Verification 766 13.9 Switch-Level Simulation 809 13.10 Transistor-Level Simulation 811 13.11 Summary 820 13.12 Problems 821 13.13 Bibliography 834 13.14 References 835 TEST 838 14.1 The Importance of Test 841 14.2 Boundary-Scan Test 843 14.3 Faults 855 14.4 Fault Simulation 865 14.5 Automatic Test-Pattern Generation 876 14.6 Scan Test 884 14.7 Built-in Self-test 887 14.8 A Simple Test Example 899 14.9 The Viterbi Decoder Example 911 14.10 Summary 914 14.11 Problems 915 14.12 Bibliography 921 14.13 References 923 ASIC CONSTRUCTION 928 15.1 Physical Design 930 15.2 CAD Tools 931 15.3 System Partitioning 935 15.4 Estimating ASIC Size 937 15.5 Power Dissipation 943 15.6 FPGA Partitioning 948 15.7 Partitioning Methods 963 15.8 Summary 978 15.9 Problems 951 15.10 Bibliography 979 15.11 References 980 FLOORPLANNING AND PLACEMENT 982 16.1 Floorplanning 986 16.2 Placement 1004 16.3 Physical Design Flow 1027 16.4 Information Formats 1023 16.5 Summary 1029 16.6 Problems 1030 16.7 Bibliography 1038 16.8 References 1039 ROUTING 1043 17.1 Global Routing 1047 17.2 Detailed Routing 1059 17.3 Special Routing 1073 17.4 Circuit Extraction and DRC 1077 17.5 Summary 1087 17.6 Problems 1088 17.7 Bibliography 1097 17.8 References 1098 VHDL RESOURCES 1103 A.1 BNF 1104 A.2 VHDL Syntax 1107 A.3 BNF Index 1125 A.4 Bibliography 1126 A.5 References 1128 VERILOG HDL RESOURCES 1132 B.1 Explanation of the Verilog HDL BNF 1133 B.2 Verilog HDL Syntax 1135 B.3 BNF Index 1154 B.4 Verilog HDL LRM 1158 B.5 Bibliography 1160 B.6 References 1162