Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing, 16)

The Mixed-Signal Boundary-Scan Test Bus is the natural complement to the widely used Boundary-Scan IEEE Std. 1149.1, commonly known as JTAG. This new Mixed-Signal standard is called IEEE Standard 1149.4 and is mainly dedicated to the manufacturing test of analog and mixed-signal boards. But like the IEEE 1149.1 it can be used for many other purposes: the test buses and their digital control form a very general `analog data highway'. Increasingly, mixed-signal boards are gaining complexity, making their testing process extremely challenging. At the same time, IC complexity and technology are getting so sophisticated that testing ICs at the board level becomes very expensive. Embedding a part of the board tester on chip is the aim of the IEEE 1149.4. Analog and Mixed-Signal Boundary-Scan is a comprehensive treatment of the design, application and structure of the IEEE 1149.4. It updates the information on digital Boundary-Scan and addresses chip designers in a dedicated chapter containing guidance to easily build analog circuits including IEEE 1149.4. A basic metrology and a test strategy with the instrumentation needed for it are also described. Analog and Mixed-Signal Boundary-Scan is essential reading for researchers and professionals who need to understand IEEE Standard 1149.4 and its practical implementation in industry.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley

Booknews

Reviews the electronic design problems that require logic equivalence checking, describes the underlying technologies that are used to solve them, and presents in detail some novel approaches to verifying design revisions after re-timing or other intensive sequential transformations. Considers symbolic, incremental, and RTL-to-gate verification. Also surveys previous and recent literature on diagnosing and correcting design error, and analyzes the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by Huang and Cheng. Double spaced. Annotation c. by Book News, Inc., Portland, Or.

Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs.
On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties.
On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.

Booknews

Electronic systems that can apply test functions for dynamic environmental effects such as electric noise, weather related conditions, and aging of components concurrently while continuing intended function are defined as capable of on-line testing. The information in these 15 contributions is largely derived from recent IEEE International On-Line Testing Workshops and covers such aspects as: self checking design, both complete systems and logic design techniques; thermal monitoring; methods of monitoring radiation that induces parametric faults through ionization; a mixed-mode self test that mixes random and deterministic tests; a self test scheme for data retention faults in memories; and two fault-tolerant systems stressing reconfiguration and component serviceability. Reprinted from , v.12, nos.1-2, February/April 1998. Annotation c. by Book News, Inc., Portland, Or.

System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is ¿any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail . System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress.
The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the same problems and occasional disagreement between authors as to definitions or the importance of factors.
... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge of that science...”.
From the Preface

Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.'... from the Foreword by Vishwani D. Agrawal

with The Ever-increasing Speed Of Integrated Circuits, Violations Of The Performance Specifications Are Becoming A Major Factor Affecting The Product Quality Level. The Need For Testing Timing Defects Is Further Expected To Grow With The Current Design Trend Of Moving Towards Deep Submicron Devices. After A Long Period Of Prevailing Belief That High Stuck-at Fault Coverage Is Sufficient To Guarantee High Quality Of Shipped Products, The Industry Is Now Forced To Rethink Other Types Of Testing.
Delay Testing Has Been A Topic Of Extensive Research Both In Industry And In Academia For More Than A Decade. As A Result, Several Delay Fault Models And Numerous Testing Methodologies Have Been Proposed. Delay Fault Testing For Vlsi Circuits Presents A Selection Of Existing Delay Testing Research Results. It Combines Introductory Material With State-of-the-art Techniques That Address Some Of The Current Problems In Delay Testing.
Delay Fault Testing For Vlsi Circuits Covers Some Basic Topics Such As Fault Modeling And Test Application Schemes For Detecting Delay Defects. It Also Presents Summaries And Conclusions Of Several Recent Case Studies And Experiments Related To Delay Testing. A Selection Of Delay Testing Issues And Test Techniques Such As Delay Fault Simulation, Test Generation, Design For Testability And Synthesis For Testability Are Also Covered.
Delay Fault Testing For Vlsi Circuits Is Intended For Use By Cad And Test Engineers, Researchers, Tool Developers And Graduate Students. It Requires A Basic Background In Digital Testing. The Book Can Used As Supplementary Material For A Graduate-level Course On Vlsi Testing.

This book contains more than the IEEE Standard 1149.4. It also contains the thoughts of those who developed the standard. Adam Osseiran has edited the original writings of Brian Wilkins, Colin Maunder, Rod Tulloss, Steve Sunter, Mani Soma, Keith Lofstrom and John McDermid, all of whom have personally contributed to this standard. To preserve the original spirit, only minor changes were made, and the reader will sense a chapter-to-chapter variation in the style of expression. This may appear awkward to some, although I found the Iack of monotonicity refreshing. A system consists of a specific organization of parts. The function of the system cannot be performed by an individual part or even a disorganized collection ofthe same parts. Testing has a system-like characteristic. Testing of a system does not follow directly from the testing of its parts, and a system built with testable parts can sometimes be impossible to test. Therefore, testability of the system must be organized. Some years ago, the IEEE published the boundary-scan Standard 1149.1. That Standard provided an architecture for digital VLSI chips. The chips designed with the 1149.1 architecture can be integrated into a testable system. However, many systems today contain both analog and digital chips. Even if all digital chips are compliant with the standard, the testability of a mixed-signal system cannot be guaranteed. The new Standard 1149.4, described in this book, extends the previous architecture to mixed-signal systems. In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech­ niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

The Mixed-Signal Boundary-Scan Test Bus is the natural complement to the widely used Boundary-Scan IEEE Std. 1149.1, commonly known as JTAG. This new Mixed-Signal standard is called IEEE Standard 1149.4 and is mainly dedicated to the manufacturing test of analog and mixed-signal boards. But like the IEEE 1149.1 it can be used for many other purposes: the test buses and their digital control form a very general `analog data highway'.
Increasingly, mixed-signal boards are gaining complexity, making their testing process extremely challenging. At the same time, IC complexity and technology are getting so sophisticated that testing ICs at the board level becomes very expensive. Embedding a part of the board tester on chip is the aim of the IEEE 1149.4.
Analog and Mixed-Signal Boundary-Scan is a comprehensive treatment of the design, application and structure of the IEEE 1149.4. It updates the information on digital Boundary-Scan and addresses chip designers in a dedicated chapter containing guidance to easily build analog circuits including IEEE 1149.4. A basic metrology and a test strategy with the instrumentation needed for it are also described.
Analog and Mixed-Signal Boundary-Scan is essential reading for researchers and professionals who need to understand IEEE Standard 1149.4 and its practical implementation in industry.

Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subjects. It is essential reading for all design and test professionals as well as researchers and students working in the field. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed. Delay Fault Testing for VLSI Circuits presents a selection of existing delay testing research results. It combines introductory material with state-of-the-art techniques that address some of the current problems in delay testing. Delay Fault Testing for VLSI Circuits is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires basic background in digital testing. The book can be used as supplementary material for a graduate-level course on VLSI testing Reviews the electronic design problems that require logic equivalence checking, describes the underlying technologies that are used to solve them, and presents in detail some novel approaches to verifying design revisions after re-timing or other intensive sequential transformations. Considers symbolic, incremental, and RTL-to-gate verification. Also surveys previous and recent literature on diagnosing and correcting design error, and analyzes the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by Huang and Cheng. Double spaced. Annotation copyrighted by Book News, Inc., Portland, OR "Analog and Mixed-Signal Boundary-Scan is a comprehensive treatment of the design, application and structure of the IEEE 1149.4. It updates the information on digital Boundary-Scan and addresses chip designers in a dedicated chapter containing guidance to easily build analog circuits including IEEE 1149.4. A basic metrology and a test strategy with the instrumentation needed for it are also described." "Analog and Mixed-Signal Boundary-Scan is essential reading for researchers and professionals who need to understand IEEE Standard 1149.4 and its practical implementation in industry."--BOOK JACKET Figure 1.1 represents an electrical circuit constructed as a printed circuit assembly (PCA) consisting of a substrate carrying a pattern of conductors (the interconnect) on which separately manufactured components are mounted so that the component pins make electrical contact with the interconnect.