80486 System Architecture (3rd Edition)

80486 System Architecture describes the hardware architecture of PC products using the Intel family of 80486 chips, providing a clear, concise explanation of the 80486 processor's relationship to the rest of the system. The author provides a comprehensive treatment of the processor including: -80486 microarchitecture and its functional units -internal and external caches -hardware interface -SL technology features -instructions new to the 80486 -the register set -486/487SX processors -486DX2 processors -486DX2 write-back enhanced processor -486DX4 processors -implementation-specific issues -main memory subsystem design -OverDrive processors If you design or test hardware or software that involves 486 processors, 80486 System Architecture is an essential, time-saving tool.The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.The PC System Architecture Series features step-by-step descriptions and instructions and accessible illustrations that enable a wide range of readers to easily understand difficult hardware topics. The authors, expert hardware training consultants for clients including IBM, Intel, Compaq, and Dell, have mastered the art of pinpointing and succinctly explaining just the critical information that PC programmers, software and hardware designers, and engineers need to know and leaving out the rest. The result is an exciting series of books that will enable readers of a wide range of backgrounds to make immediate gains in programming productivity. cover......Page 1 80486......Page 2 The MindShare Architecture Series......Page 18 Organization of This Book......Page 19 Who Should Read This Book......Page 20 Decimal Notation......Page 21 E-Mail/Phone/FAX......Page 22 Mailing Address......Page 23 License Agreement......Page 3 The Memory Bottleneck......Page 24 Disadvantage: Memory Accesses Still Bound By Bus Speed......Page 25 The Floating-Point Bottleneck......Page 26 The 80486 Microarchitecture......Page 27 The Intel Family of 486 Processors......Page 29 Introduction......Page 30 The 80486 Cache Unit......Page 32 The Instruction Pipeline/Decode Unit......Page 33 Instruction Prefetch......Page 34 The Control Unit......Page 35 The Datapath Unit......Page 36 The Memory Management Unit (MMU)......Page 37 General......Page 38 Address......Page 40 Data Bus......Page 41 Data Bus Parity......Page 42 Bus Cycle Definition......Page 43 Bus Cycle Control......Page 44 Interrupts......Page 45 Bus Arbitration......Page 46 Cache Control......Page 47 Bus Size Control......Page 49 SL Technology......Page 50 Boundary Scan Interface......Page 51 Upgrade Processor Support......Page 52 The 486 Internal Cache......Page 54 The 486 with an L2 Look-Through Cache......Page 55 Handling of Memory Reads......Page 57 Handling of Memory Reads by Another Bus Master......Page 58 Handling of Memory Writes by Another Bus Master......Page 59 When a Write-Back Policy is Used......Page 60 Summary of the L2 Look-Through Cache Designs......Page 62 The 486 with an L2 Look-Aside Cache......Page 63 The Internal Cache's View of Main Memory......Page 65 The Structure of the L1 Cache Controller......Page 66 Set the Cache Stage......Page 67 The Bus Cycle Request......Page 69 Memory Subsystem Agrees to Perform a Line Fill......Page 71 Cache Line Fill Defined......Page 72 The L2 Cache Look-Up......Page 73 Organization of the DRAM Main Memory......Page 74 The Cache Line Fill Transfer Sequence......Page 75 First Doubleword Transferred to the L2 Cache and the 80486 Microprocessor......Page 76 Transfer of the Second Doubleword to the Microprocessor......Page 77 Transfer of the Third Doubleword......Page 78 Internal Cache Update......Page 79 Burst Transfers from Four-Way Interleaved Memory......Page 81 Burst Transfers from L2 Cache......Page 83 The Interrupted Burst......Page 84 Cache Line Fill Without Bursting......Page 86 Invalidation Cycles (486 Cache Snooping)......Page 90 L1 and L2 Cache Control......Page 91 Overview of 486 Bus Cycles......Page 94 Bus Cycle Definition......Page 95 Special Cycles......Page 96 Halt Special Cycle......Page 97 Non-Burst Bus Cycles......Page 98 Address Translation......Page 99 Data Bus Steering......Page 101 Non-Cacheable Burst Reads......Page 102 Non-Cacheable Burst Writes......Page 104 Pseudo-Locked Transfers......Page 106 Transactions and BOFF# (Bus Cycle Restart)......Page 107 The Bus Cycle State Machine......Page 108 I/O Recovery Time......Page 109 General......Page 110 The Write Buffers and I/O Cycles......Page 111 Introduction to SL Technology Used in the 486 Processors......Page 112 System Management Mode (SMM)......Page 113 The SMRAM Address Map......Page 115 The System Asserts SMI......Page 118 Pending Writes are Flushed to System Memory......Page 119 Processor Saves Its State......Page 120 SMM Revision Identifier......Page 122 I/O Instruction Restart......Page 123 The Processor Enters SMM......Page 124 Exceptions and Interrupts......Page 125 Processor’s Response to RSM......Page 126 State Save Area Restored......Page 127 The Stop Grant State......Page 128 Auto-HALT Power Down......Page 130 Stop Clock Snoop State......Page 131 Changes to the Software Environment......Page 132 Instruction Set Enhancements......Page 133 Base Architecture Registers......Page 134 The System-Level Registers......Page 136 Control Register 0 (CR0)......Page 137 Alignment Mask (AM)......Page 138 Control Register 2 (CR2)......Page 139 Control Register 4 (CR4)......Page 140 Local Descriptor Table Register (LDTR)......Page 141 Virtual Paging......Page 142 The Floating-Point Registers......Page 143 The Debug and Test Registers......Page 145 Introduction to the 80486SX and 80487SX Processors......Page 148 Register Differences......Page 149 The Clock Doubler Processors......Page 152 Introduction to the Write Back Enhanced 486DX2......Page 154 The Write-Through Policy......Page 155 New Signals......Page 156 The MESI Model......Page 158 Cache Line Fill......Page 161 Bus Master Read — Processor Snoop......Page 163 Bus Master Write — Processor Snoop......Page 165 Write Back Enhanced 486DX2 System with an L2 Cache......Page 167 The L2 Cache with a Write-Through Policy......Page 168 Snoop Cycle During Cache Line Fill......Page 169 Special Cycles......Page 172 Clock Control......Page 173 Clock Multiplier......Page 176 16KB Internal Cache......Page 177 5vdc Tolerant Design......Page 179 Glossary......Page 182 Index......Page 200 Contact Mindshare......Page 206

• 80486 microarchitecture and its functional units
• internal and external caches
• hardware interface
• SL technology features
• instructions new to the 80486
• the register set
• 486/487SX processors
• 486DX2 processors
• 486DX2 write-back enhanced processor
• 486DX4 processors
• implementation-specific issues
• main memory subsystem design
• OverDrive processors

If you design or test hardware or software that involves 486 processors, 80486 System Architecture is an essential, time-saving tool.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

The PC System Architecture Series features step-by-step descriptions and instructions and accessible illustrations that enable a wide range of readers to easily understand difficult hardware topics. The authors, expert hardware training consultants for clients including IBM, Intel, Compaq, and Dell, have mastered the art of pinpointing and succinctly explaining just the critical information that PC programmers, software and hardware designers, and engineers need to know and leaving out the rest. The result is an exciting series of books that will enable readers of a wide range of backgrounds to make immediate gains in programming productivity.

Explaining the hardware architecture of PC products using the Intel 80486 chip, this book provides an explanation of the 80486 processor's relationship to the rest of the system.